期刊論文 - Xin-Yu Shih
| 出版年月 | 著作類別 | 著作名稱 | 作者 |
| Apr-24 | 期刊論文 | High-Area-Efficiency Polar Decoder Chip Architecture Reconfiguring SCL-Decoding with Reconfigurable Pipelined Sorter and SCF-Decoding with Non-Uniform 4-Segment CRC | 施信毓, 李佑辰, 李耕宏 ,謝佳翰; Xin-Yu Shih, Yu-Chen Li, Geng-Hong Li and Jia-Han Xie |
| Dec-23 | 期刊論文 | Design and Implementation of Dual-Mode Support Vector Machine (SVM) Trainer and Classifier Chip Architecture for Human Disease Detection Applications | 施信毓, 吳祥恩, 蔡明憲; Xin-Yu Shih, Hsiang-En Wu, and Ming-Xian Cai |
| Nov-23 | 期刊論文 | Unified Chip Hardware Architecture of KD-Tree Mean-Based Trainer and Speeding-Up Classifier with Repeat-Point Searching for Various Applications | 施信毓, 宋承諺, 呂曜宇; Xin-Yu Shih, Chen-Yen Song, and Yao-Yu Lu |
| Feb-23 | 期刊論文 | Design and Implementation of Decision-Tree (DT) Online Training Hardware using Divider-Free GI Calculation and Speeding-Up Double-Root Classifier | 施信毓, 邱堯, 吳祥恩; Xin-Yu Shih, Yao Chiu and Hsiang-En Wu |
| Apr-22 | 期刊論文 | Reconfigurable Hardware Architecture of Area-Efficient Multi-Mode Successive Cancellation (SC) Decoder | 施信毓, 蔡睿紘, 李秉軒, 黃繼平; Xin-Yu Shih, Jui-Hung Tsai, Bing-Xuan Li, and Chi-Ping Huang |
| Jan-19 | 期刊論文 | Flexible Design and Implementation of QC-Based LDPC Decoder Architecture for On-Line User-Defined Matrix Downloading and Efficient Decoding | 施信毓, 周宏儒; Xin-Yu Shih and Hong-Ru Chou |
| Nov-18 | 期刊論文 | Design and Implementation of Flexible and Reconfigurable SDF-Based FFT Chip Architecture with Changeable-Radix Processing Elements | 施信毓, 周宏儒, 劉岳衢; Xin-Yu Shih, Hong-Ru Chou, and Yue-Qu Liu |
| Sep-18 | 期刊論文 | Reconfigurable VLSI Design of a Changeable Hybrid-Radix FFT Hardware Architecture with 2D-FIFO Storing Structure for 3GPP LTE Systems | 施信毓, 周宏儒; Xin-Yu Shih and Hong-Ru Chou |
| Jun-18 | 期刊論文 | VLSI Design and Implementation of a Reconfigurable Hardware-Friendly Polar Encoder Architecture for Emerging High-Speed 5G System | 施信毓, 黃柏鈞, 周宏儒; Xin-Yu Shih, Po-Chun Huang, and Hong-Ru Chou |
| Jan-18 | 期刊論文 | VLSI Design and Implementation of Reconfigurable 46-Mode Combined-Radix Based FFT Hardware Architecture for 3GPP-LTE Applications | 施信毓, 周宏儒, 劉岳衢; Xin-Yu Shih, Hong-Ru Chou, and Yue-Qu Liu |
| Jun-17 | 期刊論文 | 48-Mode Reconfigurable Design of SDF FFT Hardware Architecture Using Radix-3^2 and Radix-2^3 Design Approaches | 施信毓, 劉岳衢, 周宏儒; Xin-Yu Shih, Yue-Qu Liu, and Hong-Ru Chou |
| Feb-17 | 期刊論文 | A Low-Area Fully-Reconfigurable Hardware Design of Fast Fourier Transform System for 3GPP-LTE Standard | 施信毓, 劉岳衢, 周宏儒;Xin-Yu Shih, Yue-Qu Liu, and Hong-Ru Chou |
| May-14 | 期刊論文 | A Highly-Efficient Multi-Band Multi-Mode All-Digital Quadrature Transmitter | Hua Wang, Chun-Hsien Peng, Yaopei Chang, Richard Z. Huang, Chih-Wei Chang, Xin-Yu Shih, Chia-Jui Hsu, Paul C. P. Liang, Ali M. Niknejad, IEEE Fellow, George Chien, Chao Long Tsai, and H. C. Hwang |
| 2012- | 期刊論文 | Matrix Merging Scheme and Efficient Decoding Techniques for Reconfigurable QC-LDPC Decoders | Min-An Chao, Xin-Yu Shih, and An-Yeu Andy Wu |
| Mar-08 | 期刊論文 | An 8.29mm2 52mW Multi-mode LDPC Decoder Design for Mobile WiMAX System in 0.13um CMOS Process | Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, and An-Yeu Wu |
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