會議論文- TXin-Yu Shih
| 出版年月 | 著作類別 | 著作名稱 | 作者 |
| Jul-23 | 研討會論文 | Low-Cost Hardware Design of Fast 3D-Sorter Engine for Successive Cancellation List Polar-Decoders in 5G Applications | 施信毓, 梁樂軒, 李耕宏; Xin-Yu Shih, Lok Him Samuel Leung and Geng-Hong Li |
| Oct-22 | 研討會論文 | Performance-Improved AdaBoost with Parameterized and Simple-Operation Genetic Algorithm | 施信毓, 陳柔均, 呂貞頤; Xin-Yu Shih, Rou-Jyun Chen, and Zhen-Yi Lu |
| Oct-22 | 研討會論文 | Systematic and Flexible Genetic-Algorithm-Based Feature Reduction for Decision Tree ML-Validation | 施信毓, 呂曜宇; Xin-Yu Shih and Yao-Yu Lu |
| Oct-22 | 研討會論文 | VLSI Architecture of Low-Cost High-Order Matched Filter Using 8-Phase Switching Paths for Undersea Object-Identification Applications | 施信毓, 李耕宏; Xin-Yu Shih and Geng-Hong Li |
| Jul-22 | 研討會論文 | A Systematic and Generic Correlation-Based Design Approach for Data Sample Reduction in ML-Training | 施信毓 , 吳明峻 ,吳祥恩 ; Xin-Yu Shih, Ming-Jyun Wu, and Hsiang-En Wu |
| Jul-22 | 研討會論文 | Design Methodology of Queue-Based Fast Classification for Sequential Minimal Optimization in SVM ML-Training | 施信毓 , 吳祥恩 ; Xin-Yu Shih and Hsiang-En Wu |
| Jul-22 | 研討會論文 | Design and Analysis of 7x7 Median Filter with 8-Step Low-Complexity Fast Searching Approach for Undersea Image Processing Applications | 施信毓 , 吳祥恩 ; Xin-Yu Shih and Hsiang-En Wu |
| Jul-22 | 研討會論文 | Scalable and Reconfigurable Architecture of Modified KD-Tree ML-Classifier with 5-Point Searching | 施信毓 , 宋承諺 ; Xin-Yu Shih and Chen-Yen Song |
| Nov-19 | 研討會論文 | VLSI Architecture of 36-Mode Reconfigurable FFT Hardware Chip with Newly-Developed 2D-FIFO Arrangement Structure | 施信毓; Xin-Yu Shih |
| Aug-19 | 研討會論文 | Ultra-Low-Cost VLSI Circuit of Main Computing Kernel Engine for Future Deep Learning AI-Applications | 施信毓; Xin-Yu Shih |
| Jun-19 | 研討會論文 | Hardware-Friendly Circuit of Core Sorter Computing Engine for Successive Cancellation List (SCL) Polar Decoders | 施信毓; Xin-Yu Shih |
| May-19 | 研討會論文 | Design and Analysis of Cost-Efficient Ultra-High-Order Matched Filter Architecture Using 4-Phase Calculating Paths for Underwater Applications | 施信毓; Xin-Yu Shih |
| Dec-18 | 研討會論文 | Design and Analysis of 5-Step High-Efficient Early Termination Approach for LDPC Layered Decoding in Advanced Communication Worlds | 施信毓; Xin-Yu Shih |
| Aug-18 | 研討會論文 | Innovative Hardware Architecture of High-Performance LDPC Decoder Design with Real-Time QC-LDPC Matrix Programming | 施信毓; Xin-Yu Shih |
| Jul-18 | 研討會論文 | Design and Analysis of Reduced-Operation Based 7x7 Median Filter with Innovative 4-Phase Quick Searching Approach | 施信毓; Xin-Yu Shih |
| Jul-18 | 研討會論文 | Reconfigurable VLSI Architecture of Different-Radix Based Polar Encoder Chip with Well-Arranged 2D-FIFO Planning | 施信毓; Xin-Yu Shih |
| May-18 | 研討會論文 | A Novel VLSI Architecture of Low-Area-Cost FIR-Based Matched Filter Hardware Design for Under-Water Applications | 施信毓, 劉岳衢; Xin-Yu Shih and Yue-Qu Liu |
| May-18 | 研討會論文 | A Well-Arranged FIFO-Storage Distribution Design Plan for Fully Supporting 50 Different FFT Sizes in 3GPP-LTE Communication Applications | 施信毓, 周宏儒, 陳俊強; Xin-Yu Shih, Hong-Ru Chou, and Jun-Jiang Chen |
| May-18 | 研討會論文 | Area and Speed Optimization of a 5x5 Median Filter Design with 3-Direction Fast Searching Approach for Image Signal Processing Applications | 施信毓, 周宏儒, 林昕嫻; Xin-Yu Shih, Hong-Ru Chou, and Hsin-Hsien Lin |
| May-18 | 研討會論文 | Area-Efficient VLSI Architecture of High-Order Matched Filter Design Using Odd-and-Even Phase Processing for Image Recognition Applications | 施信毓, 劉岳衢, 鄭以狄; Xin-Yu Shih, Yue-Qu Liu, and Yi-Ti Cheng |
| May-18 | 研討會論文 | VLSI Architecture of Super-High-Throughput and High-Speed K-Parallel Polar Encoder Designs for Emerging 5G Communication Applications | 施信毓, 黃柏鈞, 林凱; Xin-Yu Shih, Po-Chun Huang, and Kai Lin |
| Jan-18 | 研討會論文 | An Innovative Hardware Design of FFT Reconfigurable Computing Kernel Engine with 6 Changeable-Radix Modes for 3GPP LTE Applications | 施信毓, 劉岳衢; Xin-Yu Shih and Yue-Qu Liu |
| Jan-18 | 研討會論文 | Low-Cost and High-Speed VLSI Hardware Architecture of Discrete Pascal Transform for Signal and Image Processing Applications | 施信毓, 周宏儒; Xin-Yu Shih and Hong-Ru Chou |
| Dec-17 | 研討會論文 | Design and Analysis of Reconfigurable FFT Computing Kernel with 20 Combined-Radix Modes for 3GPP-LTE Communication Systems | 施信毓, 周宏儒; Xin-Yu Shih and Hong-Ru Chou |
| Dec-17 | 研討會論文 | XYZ-Direction Fast Minimum Searching Approach of High-Row-Weight LDPC Decoders for Advanced Communication Applications | 施信毓; Xin-Yu Shih |
| Oct-17 | 研討會論文 | A 2-D Grouping FIFO Based Hardware Architecture for Supporting 36-Mode Hybrid-Radix FFT Design in 3GPP-LTE Systems | 施信毓, 周宏儒 ; Xin-Yu Shih and Hong-Ru Chou |
| Oct-17 | 研討會論文 | Cost-Efficient Hardware Design of Coarse and Fine Rotation Based FFT Twiddle Factor Generator for 3GPP LTE Applications | 施信毓, 劉岳衢; Xin-Yu Shih and Yue-Qu Liu |
| Jun-17 | 研討會論文 | 2-Dimensional Minimum Fast-Searching Design Approach of LDPC Decoder Architecture for IEEE 802.11n/ac/ax Applications | 施信毓, 陳禹均; Xin-Yu Shih and Yu-Chun Chen |
| Jun-17 | 研討會論文 | VLSI Design of An Ultra-High-Speed Polar Encoder Architecture Using 16-Parallel Radix-2 Processing Engines for Next-Generation 5G Applications | 施信毓, 黃柏鈞;Xin-Yu Shih and Po-Chun Huang |
| Feb-17 | 研討會論文 | A Low-Area Fully-Reconfigurable Hardware Design of FFT System for 3GPP-LTE Standard | 施信毓, 劉岳衢, 周宏儒;Xin-Yu Shih, Hong-Ru Chou, and Yue-Qu Liu |
| Jan-17 | 研討會論文 | Reconfigurable Hardware Design of Low-Area-Cost Computing Kernel Engine for Different Radixes of Single-Path Delay Feedback FFT Systems | 施信毓,周宏儒; Xin-Yu Shih and Hong-Ru Chou |
| Oct-16 | 研討會論文 | High-Speed Low-Area-Cost VLSI Design of Polar Codes Encoder Architecture Using Radix-k Processing Engines | 施信毓, 黃柏鈞, 陳禹均; Xin-Yu Shih, Po-Chun Huang, and Yu-Chun Chen |
| Oct-16 | 研討會論文 | LEGO-Based VLSI Design and Implementation of Polar Codes Encoder Architecture with Radix-2 Processing Engines | 施信毓, 黃柏鈞, 陳禹均; Xin-Yu Shih, Po-Chun Huang, and Yu-Chun Chen |
| Oct-16 | 研討會論文 | Reconfigurable VLSI Design of Processing Kernel for Multiple-Radix Single-Path Delay Feedback FFT Systems | 施信毓, 周宏儒, 劉岳衢; Xin-Yu Shih, Hong-Ru Chou, and Yue-Qu Liu |
| May-13 | 研討會論文 | A highly-efficient multi-band multi-mode digital quadrature transmitter with 2D pre-distortion | Hua Wang, C.-H. Peng, Chao Lu, Yaopei Chang, Richard Huang, Andy Chang, Genie Shih, Ray Hsu, Paul C. P. Liang, SangWon Son, Ali Niknejad, George Chien, CL Tsai, and HC Hwang |
| Feb-13 | 研討會論文 | A 0.27 mm2 13.5 dBm 2.4 GHz all-digital polar transmitter using 34%-efficiency Class-D DPA in 40nm CMOS | Jie-Wei Lai, Chi-Hsueh Wang, Kaipon Kao, Anson Lin, Yi-Hsien Cho, Lanchou Cho, Meng-Hsiung Hung, Xin-Yu Shih, Che-Min Lin, Sheng-Hong Yan, Yuan-Hung Chung, Paul C.P. Liang, Guang-Kaai Dehng, Hung-Sung Li, George Chien, and Robert Bogdan Staszewski |
| Nov-09 | 研討會論文 | A Real-time Programmable LDPC Decoder Chip for Arbitrary QC-LDPC Parity Check Matrices | Xin-Yu Shih, Cheng-Zhou Zhan, and An-Yeu Wu |
| Oct-09 | 研討會論文 | A Channel-Adaptive Early Termination strategy for LDPC decoders | Yu-Hsin Chen, Yi-Ju Chen, Xin-Yu Shih, and An-Yeu Wu |
| May-09 | 研討會論文 | A Triple-Mode LDPC Decoder Design for IEEE 802.11n System | Min-An Chao, Jen-Yang Wen, Xin-Yu Shih, and An-Yeu (Andy) Wu |
| Jan-09 | 研討會論文 | A 52-mW 8.29mm2 19-mode LDPC Decoder Chip for Mobile WiMAX Applications | Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, and An-Yeu (Andy) Wu |
| Nov-08 | 研討會論文 | A 7.39mm2 76mW (1944, 972) LDPC Decoder Chip for IEEE 802.11n Applications | Xin-Yu Shih, Cheng-Zhou Zhan, and An-Yeu (Andy) Wu |
| Mar-08 | 研討會論文 | High-Performance Scheduling Algorithm for Partially Parallel LDPC Decoder | Cheng-Zhou Zhan, Xin-Yu Shih, and An-Yeu Wu |
| Jun-07 | 研討會論文 | A 19-mode 8.29mm2 52-mW LDPC Decoder Chip for IEEE 802.16e System | Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, and An-Yeu Wu |
| Nov-05 | 研討會論文 | A Triple-Mode MAP/VA IP Design for Advanced Wireless Communication Systems | Cheng-Hung Lin, Fan-Min Li, Xin-Yu Shih, and An-Yeu Wu |
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