期刊論文- Tong-Yu Hsieh
| 出版年月 | 著作類別 | 著作名稱 | 作者 | 收錄出處 |
| 2023/6/1 | 期刊論文 | Cost-effective memory protection and reliability evaluation based on machine error-tolerance: a case study on no-accuracy-loss YOLOv4 object detection model | T.-Y. Hsieh, C.-Y. Tsai, S.-J. Hou and W.-J. Chao | Microelectronics Reliability |
| 2022/7/1 | 期刊論文 | On development of reliable machine learning systems based on machine error-tolerance of input images | T.-Y. Hsieh, C.-C. Cheng, W.-J. Chao and P.-X. Wu | IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| 2020/1/1 | 期刊論文 | An implication-based test scheme for both diagnosis and concurrent error detection applications | C.-H. Wang and T.-Y. Hsieh | ACM Transactions on. Design Automation of Electronic Systems |
| 2019/5/1 | 期刊論文 | A no-reference error-tolerability test technique for videos via edge and extreme-value checking and its hardware implementation | T.-Y. Hsieh, S.-E. Chan, C.-R. Chen, P.-C. Li and C.-H. Ho | Microelectronics Reliability |
| 2018/5/1 | 期刊論文 | On probability of detection lossless concurrent error detection based on implications | C.-H. Wang and T.-Y. Hsieh | IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| 2018/2/1 | 期刊論文 | Structural variance based error-tolerability test method for image processing applications | T.-Y. Hsieh, Y.-H. Peng and K.-C. Cheng | IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems |
| 2018/1/1 | 期刊論文 | Error-tolerability enhancement via bit inversion and median filtering for single-bit errors in image processing circuits | T.-Y. Hsieh, Y.-H. Peng, K.-C. Cheng and T.-A. Cheng | Microsystem Technologies |
| 2017/8/1 | 期刊論文 | A fault-analysis oriented re-design and cost-effectiveness evaluation methodology for error tolerant applications | T.-Y. Hsieh, K.-H. Li, and C.-C. Chung | Microelectronics Journal |
| 2017/5/1 | 期刊論文 | Cost-effective enhancement on both yield and reliability for cache designs based on performance degradation tolerance | T.-Y. Hsieh, T.-L. Chih, and M.-J. Wu | IEEE Transactions on VLSI Systems |
| 2016/3/1 | 期刊論文 | An area-efficient scalable test module to support low pin-count testing | T.-Y. Hsieh, T.-P. Wang, S. Yang, C.-A. Hsu and Y.-L. Lin | IEICE Transactions on Electronics |
| 2016/2/1 | 期刊論文 | A performance degradation tolerable cache design by exploiting memory hierarchies | T.-Y. Hsieh, C.-H. Wang, T.-L. Chih, and Y.-H. Chi | IEEE Trans. on VLSI Systems |
| 2015/12/1 | 期刊論文 | Performance degradation tolerance analysis and design for effective yield enhancement | T.-Y. Hsieh, C.-H. Wang, C.-W. Kuo, S.-Y. Huang and T.-L. Chih | Journal of Electronic Testing |
| 2014/12/1 | 期刊論文 | Efficient LFSR reseeding based on internal-response feedback | W.-C. Lien, K.-J. Lee, T.-Y. Hsieh and K. Chakrabarty | Journal of Electronic Testing |
| 2014/12/1 | 期刊論文 | Efficient error-tolerability testing on image processing circuits based on equivalent error rate transformation | T.-Y. Hsieh, Y.-H. Peng and K.-H. Li | Journal of Electronic Testing |
| 2013/8/1 | 期刊論文 | Efficient on-chip test generation scheme based on programmable and multiple twisted-ring counters | W.-C. Lien, K.-J. Lee, T.-Y. Hsieh and W.-L. Ang | IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems |
| 2013/1/1 | 期刊論文 | Counter-based output selection for test response compaction | W.-C. Lien, K.-J. Lee, T.-Y. Hsieh, K. Chakrabarty and Y.-H. Wu | IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems |
| 2012/5/1 | 期刊論文 | Efficient over-detection elimination of acceptable faults for yield improvement | K.-J. Lee, T.-Y. Hsieh and M. A. Breuer | IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems |
| 2011/10/1 | 期刊論文 | Test response compaction via output bit selection | K.-J. Lee, W.-C. Lien and T.-Y. Hsieh | IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems |
| 2011/6/1 | 期刊論文 | An error-tolerance-based test methodology to support product grading for yield enhancement | T.-Y. Hsieh, K.-J. Lee and M. A. Breuer | IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems |
| 2010/7/1 | 期刊論文 | On-chip SOC test platform design based on IEEE 1500 standard | K.-J. Lee, T.-Y. Hsieh, C.-Y. Chang, Y.-T. Hong and W.-C. Huang | IEEE Trans. on VLSI Systems |
| 2008/3/1 | 期刊論文 | An error rate based test methodology to support error-tolerance | T.-Y. Hsieh, K.-J. Lee and M. A. Breuer | IEEE Trans. on Reliability |
| 2007/7/1 | 期刊論文 | Preventing over-detection of acceptable faults for yield enhancement | T.-Y. Hsieh, K.-J. Lee and M. A. Breuer | Int'l. Journal of Electrical Engineering |
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