會議論文-Jyi-Tsong Lin
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出版年月
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著作類別 | 著作名稱 | 作者 |
| Oct-24 | 研討會論文 | Comparison of Nanosheet and Fin Integration in Stacked Induced Tunnel Field-Effect Transistors | Ruei-Cheng Tu, Chia-Yo Kuo, Jyi-Tsong Lin |
| Oct-24 | 研討會論文 | Enhancing SRAM Cell Stability Through Single-Carrier CMOS Latch Integration | Yuan-Yu Chuang, Pei-Zhang Xie, and Jyi-Tsong Lin |
| Oct-24 | 研討會論文 | Impact of Gate Overlap Length Modulation on Electrical Characteristics and Subthreshold Swing in Nanosheet TFETs with Varying Tunneling Mechanisms | Zheng-Hong Zhong, Wei-Heng Tai, Jyi-Tsong Lin |
| Oct-24 | 研討會論文 | Pseudo-Parallel Symmetrical and Crossed Perovskite Solar Cells for Bifacial Applications. | Guang-Wei Huang, Hsing-Mao Cheng, Jyi-Tsong Lin |
| Oct-24 | 研討會論文 | SC-CMOS: Revolutionizing Semiconductor Technology with High Electron Mobility Materials and Advanced Node Optimization | Jyi-Tsong Lin, Pei-Zhang Xie, Yuan-Yu Chuang, Pei-Han Chen, and Wei-Han Lee |
| Aug-24 | 研討會論文 | A Novel Punch-Through nMOS for Solving Carrier Mobility Mismatch in Conventional CMOS | Pei-Zhang Xie, Jyi-Tsong Lin |
| Aug-24 | 研討會論文 | A Novel Tunnel Field-Effect Transistor with Control Source and Control Gate | Ruei-Cheng Tu, Jyi-Tsong Lin |
| Aug-24 | 研討會論文 | A Punch Through MOSFET Transistor for Low Power Supply Application | Jyi-Tsong Lin, Wei-Han Lee |
| Aug-24 | 研討會論文 | Achieving Steeper Subthreshold Swing by Novel Structure of Nanosheet Inductive Tunnel Field Effect Transistor | Hsing Kao, Jyi-Tsong Lin |
| Aug-24 | 研討會論文 | Enhanced Performance of iTFET Structures with Ge0.95Sn0.05 Pad Layer | Zheng-Hong Zhong, Jyi-Tsong Lin |
| Aug-24 | 研討會論文 | Fin-shaped Inductive Tunneling TFET with Gate-Source Overlap and Schottky Contact for Ultra-Low Power Applications | Ching-Chieh Su, Jyi-Tsong Lin |
| Aug-24 | 研討會論文 | Improving Subthreshold Swing of Novel stackable Tunnel Field Effect Transistor: Impact of Stracture and Inductive Source | Wei-Heng Tai and Jyi-Tsong Lin |
| Aug-24 | 研討會論文 | Nanosheet Integration of Induced Tunnel Field-Effect Transistor with Lower Cost and Power Consumption | Chia-Yo Kuo, Jyi-Tsong Lin |
| Aug-24 | 研討會論文 | Performance Comparisons of Novel Punch-Through PlanarFET, FinFET and GAAFET nMOSFET | Yuan-Yu Chuang, Jyi-Tsong Lin |
| Aug-24 | 研討會論文 | Schottky Junction CMOS with Schottky Junction PMOS and Schottky Junction NMOS | Jyi-Tsong Lin, Wei-Han Lee |
| Oct-23 | 研討會論文 | A Simple New Line-Tunneling iTFET with Overlapping between Gate and Source Contact | Jyi-Tsong Lin |
| Oct-23 | 研討會論文 | An iTFET with Control Gate for Low Power Applications in RF and Digital Circuits | Ho-Hin Tse, Zheng-Hong Zhong, and Jyi-Tsong Lin |
| Oct-23 | 研討會論文 | Characterization of Junction-Less TFET with Drain Schottky Barrier Contact | Jyi-Tsong Lin, Wei-Han Lee, Kuo-Tung Huang, Ruei-Kai Yang |
| Oct-23 | 研討會論文 | Steeper Subthreshold Swing Attained in Ge-Source Inductive Tunneling FET via Epitaxial Tunnel Layer for Suppressed Point Tunneling | Yen-Chen Chang, Wei-Heng Tai, and Jyi-Tsong Lin |
| Sep-20 | 研討會論文 | Performances Improvement of Tunneling Field-Effect Transistors' with the Advanced Double-Gate PN Construction | Yu-Jen Chen and Jyi-Tsong Lin |
| Apr-19 | 研討會論文 | Architecture Evaluation for Standalone and Embedded 1T-DRAM | Md. Hasan Raza Ansari;Nupur Navlakha;Jyi-Tsong Lin;Abhinav Kranti |
| Nov-18 | 研討會論文 | A New Type of Gated-PN TFET to Overcome the Ambipolar and Trap-Assisted Tunneling Effects (Invited Talk) | Jyi-Tsong Lin, Chih-Ting Yeh, Steve W. Haga, Cheng-Chun Kuo, Chun-Shuo Chou |
| Nov-18 | 研討會論文 | A Three-Terminal ZnS-based CIGS Solar Cell | Shih-Chin Huang, Jyi-Tsong Lin, Steve Haga, Wen-Hao Chen and Kung-Yu Ho |
| Nov-18 | 研討會論文 | Characterization of Double-Gate PN Type Tunneling Field-Effect Transistor | Cheng-Chun Kuo, Jyi-Tsong Lin, Chih-Ting Yeh, Abhinav Kranti |
| Nov-18 | 研討會論文 | Recessed Back-Surface-Field Crystalline Silicon Solar Cells with Heterojunction for Bifacial Application | Wen-Hao Chen, Jyi-Tsong Lin, Steve Haga, Kung-Yu Ho, and Shih-Chin Huang |
| Nov-18 | 研討會論文 | Recessed-Gate PN iTFET to Improve Subthreshold Swing and Suppress Ambipolar ( Best paper award) | Yu-Jhe Li, Jyi-Tsong Lin, Yeh-Chih Ting,Abhinav Kranti |
| Nov-18 | 研討會論文 | Symmetrical and Crossed Double-sided Passivation Emitter and Surface Field Solar Cells for Bifacial Applications | Kung-Yu Ho, Jyi-Tsong Lin, Steve Haga, Wen-Hao Chen and Shih-Chin Huang |
| Oct-18 | 研討會論文 | 1T DRAM with vertically stacked n-oxide-p architecture | Md.H.R. Ansari, N. Navlakha, J.-T. Lin, and A. Kranti |
| Oct-18 | 研討會論文 | Performance assessment of TFET architectures as 1T-DRAM | N. Navlakha, Md.H.R. Ansari, J.-T. Lin, and A. Kranti |
| Sep-18 | 研討會論文 | Influence of material parameters on the performance of accumulation mode DRAM | Md.H.R. Ansari, N. Navlakha, J.-T. Lin and A. Kranti |
| Apr-18 | 研討會論文 | Doping-less 1T-DRAM With Schottky Contact For Low Power Application | Hung-Hsiu Lin, Jyi-Tsong Lin |
| Apr-18 | 研討會論文 | A Body-Raised Punch Through MOSFET for Low Power Supply Applications | Chi-Sheng Liao, Jyi-Tsong Lin and Wei-Han Lee |
| Apr-18 | 研討會論文 | A Characteristic of iTFETs With Induced Channel Layer by Line Tunneling | Chih-Ting Yeh, Jyi-Tsong Lin |
| Apr-18 | 研討會論文 | Recessed Back-Surface-Field Crystalline Silicon Solar Cells with Heterojunction for Bifacial Application | Wen-Hao Chen, Jyi-Tsong Lin, Kung-Yu Ho, Shi-Qin Huang |
| Apr-18 | 研討會論文 | Symmetrical and Crossed Double-sided Passivation Emitter and Surface Field Solar Cells for Bifacial Applications | Jyi-Tsong Lin, Chung-Tse Lee, Wen-Hao Chen, Steve Haga, Yu-Yan Hu, and Kon-Yu Ho |
| Apr-18 | 研討會論文 | Vertical Transistor with N-Bridge and Double Gate for Low power 1T-DRAM Application | Yi-Jie Chen, Jyi-Tsong Lin, and Abhinav Kranti |
| Mar-18 | 研討會論文 | Emerging FETs for Low Power and High Speed Embedded Dynamic Random Access Memory | Md. Hasan Raza Ansari, Nupur Navlakha,Jyi-Tsong Lin,Abhinav Krant |
| Dec-17 | 研討會論文 | Investigation of Junctionless Transistor based DRAM | Md. H.R. Ansari, N. Navlakha, J.-T. Lin, and A. Kranti |
| Dec-17 | 研討會論文 | Tunnel FET Capacitorless DRAM | N. Navlakha, J.-T. Lin, and A. Kranti |
| Oct-17 | 研討會論文 | Design Optimization of Tunnel FET for Dynamic Memory Applications | Nupur Navlakha, Jyi-Tsong Lin, and Abhinav Kranti |
| Apr-17 | 研討會論文 | A Non-Classical Vertical Channel CMOS with High Performance and High Integration Density | T.-P. Hsu, J.-T. Lin, W.-H. Lee, T.-C. Wang, J.-H. Lai, C.-C. Lin, C.-Y. Yu and C.-S. Liao |
| Apr-17 | 研討會論文 | A Punch-Through DRAM for Fast Programming Time and Low Power Applications | C.-C. Lin, J.-T. Lin, A. Kranti, and C.-Y. Yu |
| Apr-17 | 研討會論文 | A Thorough Study of Trap Assisted Tunneling in Silicon TFETs | T.-C. Wang, J.-T. Lin, W.-H. Lee, C.-T. Yeh and Q.-T. Zhao |
| Apr-17 | 研討會論文 | Emitter-Wrap-Through Solar Cell with Both-Side Collection for Bifacial Application | Y.-Y. Hu, J.-T. Lin, C.-T. Lee, W.-H. Chen, K.-Y. Ho |
| Apr-17 | 研討會論文 | Non-Classical Recessed-Gate CMOS Inverter with Unique Shared Contact and Low Power Supply Applications | J.-H. Lai, J.-T. Lin, W.-H. Lee,T.-P. Hsu, and C.-S. Liao |
| Apr-17 | 研討會論文 | Twin gate Tunnel FET based capacitorless dynamic memory | Nupur Navlakha, Jyi-Tsong Lin,Abhinav Kranti |
| Apr-17 | 研討會論文 | Vertical Transistor with N-channel and Body Stack on Gate for 1T-DRAM Application | C.-Y. Yu, J.-T. Lin, C.-C. Lin, and A. Kranti |
| Dec-16 | 研討會論文 | Optimization of Back Gate Workfunction, Alignment and Bias for Charge Retention in TFET based DRAM | Nupur Navlakha, Jyi-Tsong Lin and Abhinav Kranti |
| Oct-16 | 研討會論文 | A Novel Low Bias and High Speed Non-Classical CMOS Inverter with Unique Shared Contact | Tzu-Chi Wang, Jyi-Tsong Lin*, Kai-Cheng Juang, Wei-Han Lee, Ting-Pi Hsu and Jing-Hao Lai |
| Oct-16 | 研討會論文 | A vertical and junctionless channel with T-shaped gate 1T-DRAM using new operate mechanism | Cyuan-You Yu, Jyi Tsong Lin*, Ting-Chung Chang, Chih-Chia Lin, Chih-Kai Haung and Abhinav Kranti |
| Oct-16 | 研討會論文 | Design Optimization of Tunnel Field Effect Transistor Based DRAM: A Retention Perspective | Nupur Navlakha, Jyi-Tsong Lin, and Abhinav Kranti |
| Oct-16 | 研討會論文 | Improve conventional HIT solar cell structure by using Nano-pillar | Chung-Tse Lee, Jyi-Tsong Lin, Chien-Chia Lai Po-Cheng Yan, Yu-Yan Hu |
| Oct-16 | 研討會論文 | Punch-Through Reading Mechanism and Body Raised up Structure for A Novel Punch-Through DRAM | Chih-Chia Lin,Jyi-Tsong Lin Wei-Han Lee, Chih-Kai Huang, Ting-Chung Chang and Abhinav Kranti |
| Oct-16 | 研討會論文 | Using Wet etching method to form Nano-pillar HIT solar cell with silicon-carbide-based emitter | Chung-Tse Lee, Jyi-Tsong Lin, Chien-Chia Lai |
| Oct-16 | 研討會論文 | Vertical Channel Capacitor-less One-Transistor DRAMs with a Pass-Way Trench for Improving Retention Time | Ting-Pi Hsu*1 , Jyi-Tsong Lin1, Chih-Kai Huang 1, Chih-Chia Lin 1, Abhinav Kranti2,Cyuan-You Yu1, Ting-Chung Chang1, and Po-Hsieh Lin1 |
| Sep-16 | 研討會論文 | Enhanced Retention Characteristics in Double Gate Tunnel FET based DRAM | Nupur Navlakha, Jyi-Tsong Lin, and Abhinav Kranti |
| Aug-16 | 研討會論文 | PERC Solar Cell with Local Cover Thin-Film Heterojunction | Yu-Yan Hu*, Jyi-Tsong Lin, Po-Cheng Yen, Chien-Chia Lai, Chung-Tse Lee |
| Jul-16 | 研討會論文 | Optimization of Back Gate Workfunction, Alignment and Bias for Charge Retention in TFET based DRAM | Nupur Navlakha, Jyi-Tsong Lin, and Abhinav Kranti |
| May-16 | 研討會論文 | A High Efficiency PERC Solar Cell with Local Silicon Heterojunction | Po-Cheng Yen,Jyi-Tsong Lin, Chien-Chia Lai, Yu-Yan Hu,Chung-Tse Lee |
| May-16 | 研討會論文 | A Novel High Speed Non-Classical CMOS Inverter with Unique Shared Contact for 0.5V Applications | Kai-Cheng Juang. Jyi-Tsong Lin, Wei-Han Lee,Tzu-Chi Wang, and Chung-Tse Lee |
| May-16 | 研討會論文 | A Vertical Junctionless Channel Transistor with T-shaped Gate for 1T- DRAM | Ting Chung Chang, Jyi Tsong Lin, Chih-Kai Haung, Chih-Chia Lin, Cyaan- You Yu and Abhinav Kranti |
| May-16 | 研討會論文 | A Wet-etching Nano-pillar Combined HIT Solar Cell with Silicon-Carbide-based Emitter | Chien-Chia Lai, Jyi-Tsong Lin, Po-Cheng Yen, Chung-Tse Lee, Yu-Yan Hu |
| May-16 | 研討會論文 | Enhanced Retention Characteristics and Thermal Stability of a New 1T-DRAM with An Electron-Bridge Channel Structure | Jyi-Tsong Lin, Wei-Han Lee, Po-Hsieh Lin, Steve W. Haga, Yun-Ru Chen, Dai-Rong Lu and Abhinav Kranti |
| May-16 | 研討會論文 | Vertical Channel Capacitor-less One-Transistor DRAMs with a Pass Trench for the High Performance and the Low-power Application | Chih-Kai Haung, Jyi Tsong Lin, Chih-Chia Lin, Cyaan- You Yu , Ting Chung Chang, Po-Hsieh Lin and Abhinav Kranti |
| Jan-16 | 研討會論文 | Enhanced Retention Characteristics in Double Gate Tunnel FET based DRAM | Nupur Navlakha, Jyi-Tsong Lin, and Abhinav Kranti |
| Nov-15 | 研討會論文 | A New Vertical Transistor with N-channel and Isolation Oxide for 1T-DRAM Application | Ting-Chung Chang, *Jyi-Tsong Lin, and Dai-Rong Lu, Po-Hsieh Lin and Chih-Kai Huang |
| Nov-15 | 研討會論文 | A Trench-shaped Crystalline Silicon Heterojunction Solar Cell with an Interdigitated Back Contact Structure | Po-Cheng Yen, Jyi-Tsong Lin, Jyun-Min Syu, Tzu-Hao Huang and Chien Chia ,Lai |
| Nov-15 | 研討會論文 | Novel Vertical Current Bridge SOI/Bulk MOSFETs with Gate-All-Around and Nano-Pillar Structure for 1T-DRAM Applications | Chih-Kai Huang, Jyi-Tsong Lin, Yu-Chun Wang and Po-Hsieh Lin |
| Nov-15 | 研討會論文 | Using GIDL mechanism for Low-Power Consumption and Data Retention Time Improvement in a Double-Gate Nanowire TFT 1T-DRAM with Fin-Gate and Pillar-Body Structure | Wei-Han Lee, Jyi-Tsong Lin, Yu-Chun Wang, Po-Hsieh Lin, Chien-Chia Lai, Yong-Huang Lin and Tin-Chun Chang |
| Oct-15 | 研討會論文 | “A NEW APPROACH TO WAFER SAWING: STEALTH LASER DICING TECHNOLOGY” | Yen-Chi Lee and Jyi-Tsong Lin, |
| Oct-15 | 研討會論文 | NEW STEALTH DICING METHOD WITH WLCSP APPLICATION DEVELOPMENT | Yen-Chi Lee and Jyi-Tsong Lin, |
| Sep-15 | 研討會論文 | A New Interdigitated Nanopillar HIT Solar Cell with 26.09% Efficiency Achieved by Using Silicon-Carbide-based Window Layer | Kai-Cheng Juang, Jyi-Tsong Lin, Wei-Han Lee, Ting-Chung Chang, Chih-Kai Huang, Chien-Chia Lai, Bo-Cheng Yan |
| Jul-15 | 研討會論文 | A High PCE HIT Solar Cell with Interdigitated Back Contacts | Bo-Cheng Yan*, Jyi-Tsong Lin, Jyun-Min Syu, Tzu-Hao Huang and Chien-Chia Lai |
| Jul-15 | 研討會論文 | A New Interdigitated Nanopillar HIT Solar Cell with 26.09% Efficiency by Using Silicon-Carbide-based Window Layer | Chien-Chia Lai, Jyi-Tsong Lin, Tzu-Hao Huang, Jyun-Min Syu, Bo-Cheng Yan |
| Jul-15 | 研討會論文 | A New Vertical Current Bridge One-Transistor DRAM with Gate-All-Around and Nano-Pillar Structure | Chih-Kai Huang*, Jyi-Tsong Lin, Yu-Chun Wang, Po-Hsieh Lin, Wei-Han Lee, Chien-Chia Lai and Tin-Chun Chang |
| Jul-15 | 研討會論文 | An Improved Unipolar CMOS with Elevated Body and Spacer for Low-Power Application | Wei-Han Lee, Jyi-Tsong Lin, Kai-Cheng Juang, Ting-Chung Chang, Chih-Kai Huang, Chien-Chia Lai, Bo-Cheng Yan, and Yong-Huang Lin |
| Jul-15 | 研討會論文 | An Improved Unipolar CMOS with Elevated Body and Spacer for Low-Power Application | Kai-Cheng Juang, Jyi-Tsong Lin, Wei-Han Lee, Ting-Chung Chang, Chih-Kai Huang, Chien-Chia Lai, Bo-Cheng Yan, and Yong-Huang Lin |
| Jul-15 | 研討會論文 | Novel Vertical Transistor with N-channel and Isolation Oxide for Use in 1T-DRAM | Ting Chung Chang, Jyi-Tsong Lin and Dai Rong Lu |
| Jul-15 | 研討會論文 | The Electrical Conduction Mechanisms and Characteristics of the Ni-Cr Thin Films | Nai-Chuan Chuang, Jyi-Tsong Lin, and Huey-Ru Chen, |
| Jul-15 | 研討會論文 | Using GIDL mechanism for Low-Power Consumption and Data Retention Time Improvement in a Double-Gate Nanowire TFT 1T-DRAM with Fin-Gate and Pillar-Body Structure | Wei-Han Lee*, Jyi-Tsong Lin, Yu-Chun Wang, Po-Hsieh Lin, Chien-Chia Lai, Yong-Huang Lin and Tin-Chun Chang |
| May-15 | 研討會論文 | A Steep Subthreshold Swing Technique for Gate-All-Around SOI MOSFETs | C.-Y. Chen, J. T. Lin, M.-H. Chiang and W.-C. Hsuc. |
| Oct-14 | 研討會論文 | A New Low Power Unipolar CMOS | Jyi-Tsong Lin, Steve Haga, Ming-Tsung Shih, and Yong-Huang Lin |
| Aug-14 | 研討會論文 | A NOVEL CAPACITOR-LESS DRAM WITH RAISED SOURCE STRUCTURE | Dai-Rong Lu, Jyi-Tsong Lin, Shih-Chuan Tseng, Po-Hsieh Lin, Zih-Hao Huang, Jyun-Min Syu, Yu-Chun Wang, and Yong-Huang Lin |
| Aug-14 | 研討會論文 | A NOVEL FINFET-BASED 1T-DRAM WITH EXTENDED BODY USING GATE-INDUCED DRAIN LEAKAGE MECHANISM | Zih-Hao Huang, Jyi-Tsong Lin, Po-Hsieh Lin, and Cheng-Hsien Chang |
| Aug-14 | 研討會論文 | A NOVEL NON-CLASSICAL UNIPOLAR CMOS INVERTER WITH ELEVATED BODY AND TWO EMBEDDED OXIDE | Yong-Huang Lin, Jyi-Tsong Lin, Ming-Tsung Shih, Po-Hsieh Lin, Zih-Hao Huang, Jyun-Min Syu, Dai-Rong Lu, and Yu-Chun Wang |
| Aug-14 | 研討會論文 | CHARACTERIZATION OF THE SONOS NONVOLATILE MEMORY CELL USING L-SHAPED CHANNEL STRUCTURE | Po-Hsieh Lin, Jyi-Tsong Lin, Hung-Pei Hsu, Dai-Rong Lu, and Yu-Chun Wang |
| Aug-14 | 研討會論文 | NOVEL 1T-DRAM WITH FIN-GATE AND PILLAR STRUCTURE FOR HOLE STORAGE AND DATA RETENTION TIME IMPROVEMENT | Yu-Chun Wang, Jyi-Tsong Lin, Po-Hsieh Lin, Shih-Chuan Tseng, Hung-Pei Hsu, Dai-Rong Lu, Yong-Huang Lin, Jyun-Min Syu and Zih-Hao Huang |
| Aug-14 | 研討會論文 | SIMULATION STUDY OF A NEW CAPACITOR-LESS DRAM WITH VERTICAL NANOMETER PILLAR | Jyun-Min Syu, Jyi-Tsong Lin, Chan-Hsiang Chang, Yu-Chun Wang, Dai-Rong Lu, Yong-Huang Lin, Zih-Hao Huang and Po-Hsieh Lin |
| May-14 | 研討會論文 | A New 1T-DRAM Cell with Raised Source Structure | Shih-Chuan Tseng, Jyi-Tsong Lin, Po-Hsieh Lin, Cheng-Hsien Chang, Chan-Hsiang Chang, Yu-Chun Wang, Ming-Tsung Shih, Hung-Pei Hsu and Min-Yan Lin |
| May-14 | 研討會論文 | A Novel 1T-DRAM with Fin-Gate and Pillar Structure for Excess Hole Storage and Data Retention Time Improvement | Yu-Chun Wang, Jyi-Tsong Lin, Po-Hsieh Lin, Chun-Yu Chen, Chan-Hsiang Chang, Shih-Chuan Tseng, Cheng-Hsien Chang, Hung-Pei Hsu and Dai-Rong Lu |
| May-14 | 研討會論文 | A Novel Double Gate 1T-DRAM Cell by Using Vertical Nanometer Pillar Structure | Chan-Hsiang Chang, Jyi-Tsong Lin, Po-Hsieh Lin, Cheng-Hsien Chang, Shih-Chuan Tseng, Ming-Tsung Shih, Min-Yan Lin, Hung-Pei Hsu, and Yun-Ru Chen |
| May-14 | 研討會論文 | A Novel Vertical Nanometer Pillar Structure of Double Gate 1T-DRAM | Chan-Hsiang Chang, Jyi-Tsong Lin, Po-Hsieh Lin, Cheng-Hsien Chang, Shih-Chuan Tseng, Ming-Tsung Shih, Min-Yan Lin, Hung-Pei Hsu, and Yun-Ru Chen |
| May-14 | 研討會論文 | Enhanced 1T-DRAM Performances by Using Extended Body of FinFET and Gate-induced Drain Leakage Mechanism | Cheng-Hsien Chang, Jyi-Tsong Lin, Po-Hsieh Lin, Chan-Hsiang Chang, Shih-Chuan Tseng, Ming-Tsung Shih, Min-Yan Lin, and Hung-Pei Hsu |
| May-14 | 研討會論文 | Enhanced 1T-DRAM Transient characteristics By Using Wide Trench-Body Structure | Po-Hsieh Lin and Jyi-Tsong Lin |
| May-14 | 研討會論文 | Enhanced Retention Characteristics of New 1T-DRAM Using NPO Structure | Po-Hsieh Lin, Jyi-Tsong Lin, IEEE Senior Member, Yun-Ru Chen, Chan-Hsiang Chang, and Cheng-Hsien Chang |
| May-14 | 研討會論文 | Improved 1T-DRAM Performances by Using FinFET with Extended Body Structure | Cheng-Hsien Chang, Jyi-Tsong Lin, Po-Hsieh Lin, Chan-Hsiang Chang, Shih-Chuan Tseng, Ming-Tsung Shih, Min-Yan Lin, and Hung-Pei Hsu |
| May-14 | 研討會論文 | Improved Electrical Characteristics of Non-classical Unipolar CMOS Using Elevated Body and Two Embedded Oxide | Ming-Tsung Shih, Jyi-Tsong Lin, Shih-Chuan Tseng, Cheng-Hsien Chang, Min-Yan Lin, Chan-Hsiang Chang, and Hung-Pei Hsu |
| May-14 | 研討會論文 | Improvement of 1T-DRAM Transient Characteristics By Using NPO Structure | Po-Hsieh Lin, Jyi-Tsong Lin, Yun-Ru Chen, Chan-Hsiang Chang, Cheng-Hsien Chang, and Shih-Chuan Tseng |
| May-14 | 研討會論文 | Investigation of Novel MOSFET Structure with Raised Source for 1T- DRAM Application | Shih-Chuan Tseng, Jyi-Tsong Lin, Po-Hsieh Lin, Cheng-Hsien Chang, Chan-Hsiang Chang, Yu-Chun Wang, Ming-Tsung Shih, Hung-Pei Hsu and Min-Yan Lin |
| May-14 | 研討會論文 | L-MOS Study on SONOS-type Nonvolatile Memory | Hung-Pei Hsu, Jyi-Tsong Lin, Po-Hsieh Lin, Cheng-Hsien Chang, Ming-Tsung Shih, Chan-Hsiang Chang, Shih-Chuan Tseng, Min-Yan Lin, and Shih-Wen Hsu |
| May-14 | 研討會論文 | Simulation Study of a Novel Non-classical Unipolar CMOS Inverter with Elevated Body and Two Embedded Oxide | Ming-Tsung Shih, Jyi-Tsong Lin, Shih-Chuan Tseng, Cheng-Hsien Chang, Min-Yan Lin, Chan-Hsiang Chang, and Hung-Pei Hsu |
| May-14 | 研討會論文 | Simulation Study of an a-Si:H/SiGe Heterojunction Solar Cells | Min-Yan Lin, Jyi-Tsong Lin, Jyun-Min Syu, Zih-Hao Huang, Shih-Chuan Tseng, Ming-Tsung Shih, Cheng-Hsien Chang, Hung-Pei Hsu, Chan-Hsiang Chang |
| May-14 | 研討會論文 | Study of L-SONOS with Different Channel Structure | Hung-Pei Hsu, Jyi-Tsong Lin, Po-Hsieh Lin, Shih-Wen Hsu, Cheng-Hsien Chang,Ming-Tsung Shih, Shih-Chuan Tseng, Chan-Hsiang Chang, and Min-Yan Lin |
| May-14 | 研討會論文 | Study of an a-Si:H/SiGe Heterojunction Solar Cells | Min-Yan Lin, Jyi-Tsong Lin, Jyun-Min Syu, Zih-Hao Huang, Shih-Chuan Tseng, Ming-Tsung Shih, Cheng-Hsien Chang, Hung-Pei Hsu, Chan-Hsiang Chang |
| Nov-13 | 研討會論文 | A Novel High Integration-Density TFT-CMOS Inverter with Vertical Structure for Low Power Application | Min-Yan Lin, Jyi-Tsong Lin, and You-Ren Lu |
| Nov-13 | 研討會論文 | An Investigation of the SONOS with Side-Block Oxide for Non-Volatile Memory | Shih-Chuan Tseng, Jyi-Tsong Lin, and Shih-Wen Hsu |
| Oct-13 | 研討會論文 | Comparative Study of Process Variations in Junctionless and Conventional Double-Gate MOSFETs | Chun-Yu Chen, Jyi-Tsong Lin, and Meng-Hsueh Chiang |
| Sep-13 | 研討會論文 | A High Speed Triple-Gate 1T-DRAM with Middle Partial Insulation for Embedded Memory Application | Chan-Hsiang Chang, Jyi-Tsong Lin, Yun-Ru Chen |
| Sep-13 | 研討會論文 | A Study of High Speed and Low Cost Non-Classical Unipolar CMOS | Ming-Tsung Shih, Jyi-Tsong Lin, Kuan-Yu Chen |
| Jun-13 | 研討會論文 | A Novel 14 nm Extended Body FinFET for Reduced Corner Effect, Leakage Current and Improved Self-Heating Effect | Cheng-Hsien Chang, Jyi-Tsong Lin, Po-Hsieh Lin |
| Jun-13 | 研討會論文 | Characterization of the LMOS with different channel structure | Hung-Pei Hsu, Jyi-Tsong Lin, Po-Hsieh Lin |
| Jun-13 | 研討會論文 | Thermal Stability of a Vertical SOI-Based Capacitorless One-Transistor DRAM | Po-Hsieh Lin and Jyi-Tsong Lin |
| Apr-13 | 研討會論文 | A New Type of CMOS Inverter with Gated-IIP Load and TFET Driver for 22nm Node Technology | Hsueh-Liang Huang, Jyi-Tsong Lin, Chen-Chi Tsai, Kuan-Yu Chen,You-Ren Lu,Shih-Wen Hsu,and Po-Hsieh Lin |
| Apr-13 | 研討會論文 | A Novel Bulk Triple-Gate 1T-DRAM with Middle Partial Insulation and Current Bridge for 22 nm Technology node | Yun-Ru Chen, Jyi-Tsong Lin, Po-Hsieh Lin and Shih-Wen Hsu |
| Apr-13 | 研討會論文 | A Novel Non-classical CMOS Inverter Composed of a NMOS and a Junction-less PMOS Transistor for Low Power Application | Chen-Chi Tsai*, Jyi-Tsong Lin |
| Apr-13 | 研討會論文 | A Novel TFT-CMOS Inverter for ULSI applications | You-Ren Lu, Jyi-Tsong Lin, Yi-Chuen Eng, Shih-Wen Hsu, Shu-Huan Syu, and Kuan-Yu Chen |
| Apr-13 | 研討會論文 | A Study of Non-Classical Unipolar CMOS with Double-Embedded Oxide and Elevated Body | Kuan-Yu Chen, Jyi-Tsong Lin, Hseuh-Liang Huang, Shih-Wen Hsu, Shu-Huan Syu, and You-Ren Lu |
| Apr-13 | 研討會論文 | Design Insights of Si Nanowire FETs: A Simulation-Based Study | Chun-Yu Chen, Jyi-Tsong Lin and Meng-Hsueh Chiang |
| Apr-13 | 研討會論文 | Simulation Study of Partial-Oxide Junctionless and Junction Vertical MOSFET | Shu-Huan Syu, Jyi-Tsong Lin and Yi-Chuen Eng |
| Apr-13 | 研討會論文 | Simulation of A Novel Single Junction Thin Film Solar Cell | Wan-Rou Chang*, Jyi-Tsong Lin, Yi-Chuen Eng, Yu-Sheng Kuo, Yun-Ru Chen, Po-Hsieh Lin and Jian-Yuan Wang |
| Apr-13 | 研討會論文 | Study of Vertical SOI-Based 1T-DRAM with Trench-Body Structure | Po-Hsieh Lin, Jyi-Tsong Lin, Yi-Chuen Eng, and Yun-Ru Chen |
| Apr-13 | 研討會論文 | Study of a CIGS Thin Film Solar Cell with Dual Absorber Layers | Jian-Yuan Wang*, Jyi-Tsong Lin, Yu-Sheng Kuo |
| Apr-13 | 研討會論文 | Study of a SONOS with Block Oxide for Non-Volatile Memory Applications | Shih-Wen Hsu, Jyi-Tsong Lin, Yun-Ru Chen, Shu-Huan Syu, Kuan-Yu Chen, and You-Ren Lu |
| Feb-13 | 研討會論文 | Simulation of a novel single junction thin film solar cell | Wan-Rou Chang, Jyi-Tsong Lin, Yi-Chuen Eng, Yu-Sheng Kuo, Yun-Ru Chen, Po-Hsieh Lin and Jian-Yuan Wang |
| Jan-13 | 研討會論文 | Microscopic Study of Random Dopant Fluctuation in Silicon Nanowire Transistors Using 3D Simulation | Chun-Yu Chen, Jyi-Tsong Lin and Meng-Hsueh Chiang |
| Nov-12 | 研討會論文 | Impact of Discrete Random Dopant on “Undoped” Silicon Nanowire Transistors | Chun-Yu Chen, Jyi-Tsong Lin, and Meng-Hsueh Chiang |
| Oct-12 | 研討會論文 | A CIGS Thin Film Solar Cell with Dual Absorber Layers | Jian-Yuan Wang, Jyi-Tsong Lin, Yu-Sheng Kuo, Ching-yao Pai, Yi-Chuen Eng |
| Oct-12 | 研討會論文 | A New GaP/a-Si:H/Bulk Solar Cell | Jian-Yuan Wang, Jyi-Tsong Lin, Ching-yao Pai, Yu-Sheng Kuo, Yi-Chuen Eng, Po-Hsieh Lin |
| Oct-12 | 研討會論文 | A Novel 30 nm Self-Aligned Bottom-Gate MOSFET with Edged Source/Drain-Tie | Chen-Chi Tsai, Jyi-Tsong Lin, Yi-Chuen Eng, and Po-Hsieh |
| Oct-12 | 研討會論文 | Simulation study of junctionless vertical mosfets for analog applications | Shu-Huan Syu, Jyi-Tsong Lin, Yi-Chuen Eng, Shih-Wen Hsu, Kuan-Yu Chen, and You-Ren Lu |
| Jun-12 | 研討會論文 | 2-DSimulation Study of Analog Performance of Junction and Junctionless Poly-Si TFTs | Shih-Wei Wang, Jyi-Tsong Lin, Yi-Chuen Eng, Chia-Hsien Lin, Hsuan-Hsu Chen, Po-Hsieh Tai, Ching-Yao Pai |
| Jun-12 | 研討會論文 | A CIGS Thin Film Solar Cell with an InGaP Secondary Absorption Layer | Yu-Sheng Kuo, Jyi-Tsong Lin, Yi-Chuen Eng, Ching-Yao Pai |
| Jun-12 | 研討會論文 | A study of Novel Unipolar CMOS Inverter Utilizing the Punch-Through Effect | Chia-Hsien Lin, Jyi-Tsong Lin, Hsuan-Hsu Chen, and Shih-Wei Wang |
| Jun-12 | 研討會論文 | Analog Performance of a Block-Oxide Source/Drain-Tied Polycrystalline Silicon Thin-Film Transistor with Additional Polycrystalline Silicon Body | Yi-Chuen Eng and Jyi-Tsong Lin |
| Jun-12 | 研討會論文 | Investigation of Short-Channel Effects in Self-Aligned Dual-Channel Source/Drain-Tied MOSFETs | You-Ren Lu; Jyi-Tsong Lin; Yi-Chuen Eng; Shih-Wen Hsu; Shu-Huan Syu; Kuan-Yu Chen |
| Jun-12 | 研討會論文 | Numerical Study of the GaP/Si Solar Cell | Ching-Yao Pai, Jyi-Tsong Lin, Yi-Chuen Eng, Yu-Sheng Kuo |
| May-12 | 研討會論文 | A Simulation Discussion of Junction and Junctionless Vertical MOSFETs by Using Partial SOI Process | Shu-Huan Syu, Jyi-Tsong Lin, Yi-Chuen Eng, Shih-Wen Hsu, Kuan-Yu Chen, and You-Ren Lu |
| May-12 | 研討會論文 | Characterization of a New L-Shaped MOSFET for Future Deca Nano Application | Po-Hsieh Lin, Jyi-Tsong Lin |
| May-12 | 研討會論文 | Design, Simulation, and Fabrication of a New Poly-Si Based Capacitor-less 1T-DRAM Cell | Yun-Ru Chen, Jyi-Tsong Lin, Tzu-Feng Chang, Yi-Chuen Eng, Po-Hsieh Lin, and Cheng-Hsin Chen |
| May-12 | 研討會論文 | Junction vs. Junctionless Vertical MOSFET by Using Partial SOI Structure: A 2D Simulation Study | Shu-Huan Syu, Jyi-Tsong Lin, Yi-Chuen Eng, Shih-Wen Hsu, Kuan-Yu Chen, and You-Ren Lu |
| May-12 | 研討會論文 | Short-Channel Characteristics of Self-Aligned Dual-Channel Source/Drain-Tied MOSFETs | You-Ren Lu; Jyi-Tsong Lin; Yi-Chuen Eng; Shih-Wen Hsu; Shu-Huan Syu; Kuan-Yu Chen |
| May-12 | 研討會論文 | Simulation Study of Junctionless Vertical MOSFETs for Analog Applications | Shih-Wen Hsu, Jyi-Tsong Lin, Yi-Chuen Eng, Shu-Huan Syu, Kuan-Yu Chen, and You-Ren Lu |
| May-12 | 研討會論文 | Simulation Study of Junctionless Vertical MOSFETs for Analog Applications | Shih-Wen Hsu, Jyi-Tsong Lin, Yi-Chuen Eng, Shu-Huan Syu, Juan-Yu Chen, and You-Ren Lu |
| May-12 | 研討會論文 | The Effects of Block Oxide Length (Lbo) and Height (Hbo) in a bMOS | Kuan-Yu Chen, Jyi-Tsong Lin, Yi-Chuen Eng, Shih-Wen Hsu, Shu-Huan Syu, and You-Ren Lu |
| May-12 | 研討會論文 | The Effects of Block Oxide Length (Lbo) and Height (Hbo) in a bMOS Transistor: A Junction Discussion | Kuan-Yu Chen, Jyi-Tsong Lin, Yi-Chuen Eng, Shih-Wen Hsu, Shu-Huan Syu, and You-Ren Lu |
| Apr-12 | 研討會論文 | A 2-D Simulation Study of Junctionless Vertical Devices for Analog Applications | Shih-Wen Hsu, Jyi-Tsong Lin, Yi-Chuen Eng, Shu-Huan Syu, Juan-Yu Chen, and You-Ren Lu |
| Apr-12 | 研討會論文 | A Novel Pseudo-CMOS for all-NMOS Application | Jyi-Tsong Lin, Hsuan-Hsu Chen, Chen-Chi Ysai, and Kuan-Yu Lu |
| Apr-12 | 研討會論文 | A Novel Unipolar CMOS Inverter Utlizing the Punch-Through Effect | Chia-Hsien Lin, Jyi-Tsong Lin, Hsuan-Hsu Chen, and Shih-Wei Wang |
| Apr-12 | 研討會論文 | A discussion of a bMOS Transistor by Changing the Block Oxide Length (Lbo and Height (Hbo)) | Kuan-Yu Chen, Jyi-Tsong Lin, Yi-Chuen Eng, Shih-Wen Hsu, Shu-Huan Syu, and You-Ren Lu |
| Apr-12 | 研討會論文 | A study of the Partial Vertical SOI-Based MOSFETs with/without Junction | Shu-Huan Syu, Jyi-Tsong Lin, Yi-Chuen Eng, Po-Hsieh Lin, Shih-Wen Hsu, Kuan-Yu Chen, and You-Ren Lu |
| Apr-12 | 研討會論文 | Fabricationand Device Characterization of a Block-Oxide Source/Drain-Tied Polycrystalline Silicon Thin-Flim Transistor with Additional Polycrystalline Silicon Body | Yi-Chuen Eng, Jyi-Tsong Lin, Yi-Hsuan Fan |
| Apr-12 | 研討會論文 | Study of a New L-Shaped MOSFET for Future Deca Nano Application | Po-Hsieh Lin, and Jyi-Tsong Lin |
| Nov-11 | 研討會論文 | A Qualitative Comparison Study of Analog Performance of Junction and Junctionless Poly-Si TFTs | Shih-Wei Wang*, Jyi-Tsong Lin, Yi-Chuen Eng , Yu-Che Chang, Chia-Hsien Lin, Hsuan-Hsu Chen, Po-Hsieh Lin, Chih-Hsuan Tai, Ching-Yao Pai |
| Nov-11 | 研討會論文 | Capacitance Modeling for Silicon Nanowire MOSFETs | Chun-Yu Chen, Jyi-Tsong Lin, Meng-Hsueh Chiang, Yi-Chuen Eng and Hsun Li |
| Nov-11 | 研討會論文 | Unipolar CMOS Inverter Based on Punch-Through Effect with Two Embedded Oxide Structure | Chia-Hsien Lin, Jyi-Tsong Lin, Hsuan-Hsu Chen, Yi-Chuen Eng, Shih-Wei Wang |
| Oct-11 | 研討會論文 | A Unipolar-CMOS with Recessed Source/Drain Load | Jyi-Tsong Lin, Hsuan-Hsu Chen, Kuan-Yu Lu, Chih-Hung Sun, Tung-Yen Lai, Fu-Liang Yang |
| Jun-11 | 研討會論文 | A Novel Non-Classical Unipolar CMOS with Raised HalfGate Structure and Oxide Trench | Chih-Hsuan Tai, Jyi-Tsong Lin, and Yi-Chuen Eng |
| Jun-11 | 研討會論文 | Characteristics of a Trench Oxide Insulation Polysilicon Thin-Film Transistor | Cheng-Hsin Chen, Jyi-Tsong Lin, Tzu-Feng Chang, Yi-Chuen Eng, Po-Hsieh Lin |
| Jun-11 | 研討會論文 | Characterization of a New L-Shaped MOSFET for Future Deca-Nano Application | Po-Hsieh Lin, Jyi-Tsong Lin, Yi-Chuen Eng, and Yu-Che Chang |
| Jun-11 | 研討會論文 | Influence of Additional-Body Effects on Electrical Characteristics of Ultrathin-Body and Buried Oxide (UTBB) SOI MOSFETs: A 3D Simulation Study | Yi-Chuen Eng, Jyi-Tsong Lin, Cheng-Hsin Chen, and Yi-Hsuan Fan |
| Jun-11 | 研討會論文 | Investigation of Highly Scaled Dual-Channel Source/Drain-Tied MOSFET with Extremely Thin Body | Yi-Hsuan Fan, Jyi-Tsong Lin , and Yi-Chuen Eng |
| May-11 | 研討會論文 | A New Unipolar CMOS Comprising a Load MOSFET with Two-Embedded Oxides | Chia-Hsien Lin, Jyi-Tsong Lin, Hsuan-Hsu Chen, Yi-Chuen Eng, Po-Hsieh Lin, Shih-Wei Wang, Kuan-Yu Lu, Chih-Hsuan Tai |
| May-11 | 研討會論文 | Characterization of a New Junction-less Thin Film Transistor | Ching-Yao Pai, Jyi-Tsong Lin, Shih-Wei Wang, Chia-Hsien Lin, Yu-Sheng Kuo, Yi-Chuen Eng, Po-Hsieh Lin, Yi-Hsuan Fan, Chih-Hsuan Tai, Hsuan-Hsu Chen, Cheng-Hsin Chen, and Kuan-Yu Lu |
| Apr-11 | 研討會論文 | A New Non-Classical Unipolar CMOS with 2-Embedded Oxide | Chia-Hsien Lin, Jyi-Tsong Lin, Hsuan-Hsu Chen, Yi-Chuen Eng, Po-Hsieh Lin, Shih-Wei Wang, Kuan-Yu Lu, Chih-Hsuan Tai |
| Apr-11 | 研討會論文 | A Novel Complementary Inverter Composed of a TFET and a Gated P-I-N Transistor | Kuan-Yu Lu, Jyi-Tsong Lin, Hsuan-Hsu Chen, Yi-Chuen Eng |
| Apr-11 | 研討會論文 | A Novel TFT with Airgap-Insulated and Trenched Body Structure For 1T-DRAM Application | Cheng-Hsin Chen, Jyi-Tsong Lin, Tzu-Feng Chang, Yi-Chuen Eng, Po-Hsieh Lin, Yu-Che Chang |
| Apr-11 | 研討會論文 | A Novel Three-Dimensional Fold-Up Non-Classical Unipolar CMOS Structure and Its New Mechanism | Hsuan-Hsu Chen, Jyi-Tsong Lin, Chih-Hao Kuo, Chih-Hung Sun, Yi-Chuen Eng, Tzu-Feng Chang, Po-Hsieh Lin, and Hsien-Nan Chiu |
| Apr-11 | 研討會論文 | Characterisation of a New Polysilicon Thin-Film Transistor with Trench Oxide Layer and its 1T-DRAM Applications | Yu-Che Chang, Jyi-Tsong Lin*, Hsien-Nan Chiu, Yi-Chuen Eng, Cheng-Hsin Chen, and Po-Hsieh Lin |
| Apr-11 | 研討會論文 | Characterization of a Planar Body-Connected FinFET | Po-Hsieh Lin, Jyi-Tsong Lin, Yi-Chuen Eng, |
| Apr-11 | 研討會論文 | Investigation of Temperature Variation Effects in Ultra-Thin Body and Buried Oxide (UT2B) for a Novel Dual-Channel Source/Drain-Tied MOSFET | Yi-Hsuan Fan, Jyi-Tsong Lin, and Yi-Chuen Eng |
| Apr-11 | 研討會論文 | Numerical Study for Scaled-Down Characteristics of the Junctionless Vertical MOSFET and the Junction Vertical MOSFET | Chih-Hsuan Tai, Jyi-Tsong Lin, and Yi-Chuen Eng |
| Mar-11 | 研討會論文 | RF Performance of the Novel Planar-Type Body-Connected FinFET Fabricated by Isolation-Last and Self-Alignment Process | Po-Hsieh Lin, Jyi-Tsong Lin, Yi-Chuen Eng, Yu-Che Chang |
| Mar-11 | 研討會論文 | RF Performance of the Novel Planar-Type Body-Connected FinFET Fabricated by Isolation-Last and Self-Alignment Process | Po-Hsieh Lin, Jyi-Tsong Lin, Yi-Chuen Eng, Yu-Che Chang |
| Nov-10 | 研討會論文 | A New STI–type FinFET Device Structure for High-Performance Applications | Jyi-Tsong Lin, Po-Hsieh Lin, and Yi-Chuen Eng |
| Nov-10 | 研討會論文 | A New TFT with Trenched Body and Airgap-Insulated Structure for 3D Capacitorless 1T-DRAM Application | Jyi-Tsong Lin, Tzu-Feng Chang*, Yi-Chuen Eng, Chih-Hung Sun, Hsien-Nan Chiu, Chun-Yu Chen, Chih-Hao Kuo, Hsuan-Hsu Chen, Po-Hsieh Lin |
| Nov-10 | 研討會論文 | A New Type of CMOS Inverter with Lubistor Load and TFET Driver for Sub-20 nm Technology Generation | Hsuan-Hsu Chen, Jyi-Tsong Lin, Kuan-Yu Lu, Yi-Chuen Eng, Po-Hsieh Lin |
| Nov-10 | 研討會論文 | A New Type of CMOS Inverter with Lubistor load and NMOS Driver | Jyi-Tsong Lin, Hsuan-Hsu Chen, Kuan-Yu Lu, and Cheng-Hsin Chen |
| Nov-10 | 研討會論文 | A Novel CMOS Inverter Composed of a Junctionless NMOSFET and a Gated N--N-P+ Transistor for ULSI applications | Kuan-Yu Lu, Jyi-Tsong Lin, Hsuan-Hsu Chen, Yi-Chuen Eng |
| Nov-10 | 研討會論文 | A Novel Dual-Channel Body-Tied MOSFET with Self-Aligned Structure for Analog/RF Applications | Yi-Hsuan Fan, Jyi-Tsong Lin, Yi-Chuen Eng, Yu-Che Chang, Cheng-Hsin Chen, Kuan-Yu Lu, and Chih-Hsuan Tai |
| Nov-10 | 研討會論文 | A Novel High-Performance Junctionless Vertical MOSFET Produced on Bulk-Si Wafer | Chih-Hsuan Tai, Jyi-Tsong Lin, Yi-Chuen Eng, Po-Hsieh Lin |
| Nov-10 | 研討會論文 | A Novel Planar-type Body-Connected FinFET Device Fabricated by Self-Align Isolation-Last Process | Po-Hsieh Lin, Jyi-Tsong Lin, Yu-Che Chang, Yi-Chuen Eng, Hsuan-Hsu Chen |
| Nov-10 | 研討會論文 | A Novel Vertical MOSFET with bMPI Structure for 1T-DRAM Application | Cheng-Hsin Chen*, Jyi-Tsong Lin, Yi-Chuen Eng, Po-Hsieh Lin, Hsien-Nan Chiu, Tzu-Feng Chang |
| Nov-10 | 研討會論文 | A Novel Vertical MOSFET with bMPI Structure for 1T-DRAM Applications: A 2-D Numerical Study | Cheng-Hsin Chen, Jyi-Tsong Lin, Yi-Chuen Eng, Po-Hsieh Lin |
| Nov-10 | 研討會論文 | A Numerical Study of RF Performance for A Junctionless Vertical MOSFET | Chih-Hsuan Tai, Jyi-Tsong Lin, Yi-Chuen Eng |
| Nov-10 | 研討會論文 | A Simulation Study of Junctionless Pseudo Tri-gate Vertical MOSFETs for RF/Analog Applications | Yu-Che Chang, Jyi-Tsong Lin, Yi-Chuen Eng |
| Nov-10 | 研討會論文 | An Influence of Temperature Variation for the DC and RF/analog Performance in a Novel Dual-Channel Source/Drain-Tied MOSFET | Yi-Hsuan Fan, Jyi-Tsong Lin, and Yi-Chuen Eng |
| Nov-10 | 研討會論文 | Characterisation of New Vertical MOSFETs with Recessed Gate | Chih-Hao Kuo, Jyi-Tsong Lin *, Yi-Chuen Eng, and Yi-Hsuan Fan |
| Nov-10 | 研討會論文 | Characteristics of a New Trench-Oxide Thin-Film Transistor and its 1T-DRAM Applications | Hsien-Nan Chiu, Jyi-Tsong Lin, Yi-Chuen Eng, Tzu-Feng Chang, Chih-Hung Sun, Po-Hiesh Lin, Chih-Hao Kuo, Hsuan-Hsu Chen, Cheng-Hsin Chen |
| Nov-10 | 研討會論文 | Characterization for Novel Non-traditional CMOS Inverter Composed of a Junctionless NMOSFET and a Gated N+-N--P Transistor | Kuan-Yu Lu, Jyi-Tsong Lin, Hsuan-Hsu Chen, Yi-Chuen Eng, Chih-Hsuan Tai, Cheng-Hsin Chen |
| Nov-10 | 研討會論文 | DC Characteristics of High Performance Self-Aligned Bulk-Si Dual-Channel Source/Drain-Tied MOSFETs | Yi-Hsuan Fan, Jyi-Tsong Lin, and Yi-Chuen Eng |
| Nov-10 | 研討會論文 | Electrical Characterization of 10-nm Π-Shaped S/D MOSFETs | Yi-Chuen Eng, Jyi-Tsong Lin, Yi-Hsuan Fan, Po-Hsieh Lin, Chih-Hao Kuo, Yu-Che Chang, Kuan-Yu Lu, Cheng-Hsien Chen, and Chih-Hsuan Tai |
| Nov-10 | 研討會論文 | High Performance Junctionless PTGVMOS with Native Tie for Deca-nanometer Regime | Yu-Che Chang, Jyi-Tsong Lin, Yi-Chuen Eng, Po-Hsieh Lin |
| Nov-10 | 研討會論文 | Highly Scaled Block Oxide Bulk-MOSFETs with Excellent Short-Channel Characteristics | Yi-Chuen Eng, Jyi-Tsong Lin |
| Nov-10 | 研討會論文 | Numerical Study of Non-Classical Unipolar CMOS with different Embedded Oxide and Gate length | Chih-Hung Sun, Jyi-Tsong Lin, Hsuan-Hsu Chen, Yi-Chuen Eng, Chih-Hao Kuo, Tze-Feng Chang |
| Nov-10 | 研討會論文 | Numerical Study of Performance Comparison between Junction and Junctionless Thin-Film Transistors | Ching-Yao Pai, Jyi-Tsong Lin, Shih-Wei Wang, Chia-Hsien Lin, Yu-Sheng Kuo, Yi-Chuen Eng, Po-Hsieh Lin, Yi-Hsuan Fan, Chih-Hsuan Tai, Hsuan-Hsu Chen, Cheng-Hsin Chen, Kuan-Yu Lu |
| Nov-10 | 研討會論文 | Numerical Study of a Non-Classical Unipolar CMOS with Embedded Oxide | Chih-Hung Sun, Jyi-Tsong Lin, Hsuan-Hsu Chen, Yi-Chuen Eng, Chih-Hao Kuo, Tze-Feng Chang, Chun-Yu Chen, Po-Hsieh Lin, Hsien-Nan Chiu |
| Nov-10 | 研討會論文 | RF Performance of the Novel STI-Type Body-Connected FinFET | Po-Hsieh Lin, Jyi-Tsong Lin, and Yi-Chuen Eng |
| Nov-10 | 研討會論文 | RF/Analog Performance of Novel Junctionless Vertical MOSFETs | Chih-Hsuan Tai, Jyi-Tsong Lin, and Yi-Chuen Eng |
| Nov-10 | 研討會論文 | Reliability Analysis of a New Vertical MOSFET with bMPI Structure for 1T-DRAM Applications | Cheng-Hsin Chen*, Jyi-Tsong Lin, Po-Hsieh Lin, Yi-Chuen Eng, Hsien-Nan Chiu, Tzu-Feng Chang, Hsuan-Hsu Chen |
| Nov-10 | 研討會論文 | Study of Junctionless Pseudo Tri-gate Vertical MOSFETs for RF/analog Applications | Yu-Che Chang, Jyi-Tsong Lin, Yi-Chuen Eng, Cheng-Hsin Chen |
| Oct-10 | 研討會論文 | High-Performance Ultra-Low Power Junctionless Nanowire FET on SOI Substrate in Subthreshold Logic Application | Chun-Yu Chen, Jyi-Tsong Lin and Meng-Hsuch Chiang |
| Sep-10 | 研討會論文 | A New Design Window of Fully Depleted Si Nanowire FET | Chun-Yu Chen, Jyi-Tsong Lin and Meng-Hsuch Chiang |
| Aug-10 | 研討會論文 | Realization of Unipolar-CMOS | Jyi-Tsong Lin, Hsuan-Hsu Chen, Kuan-Yu Lu, Chih-Hung Sun, Yi-Chuen Eng, Chih-Hao Kuo, Po-Hsieh Lin, Tung-Yen Lai, Fu-Liang Yang |
| Jul-10 | 研討會論文 | A 3-D Simulation Study of A Novel Vertical MOSFET with Source-Tied (STVMOS) | Chih-Hsuan Tai, Jyi-Tsong Lin, Yi-Chuen Eng, Kuan-Yu Lu, Cheng-Hsin Chen, Yu-Che Chang, and Yi-Hsuan Fan |
| Jul-10 | 研討會論文 | Thermal Characteristics of an Advanced bMPI-based 1T-DRAM Cell | Cheng-Hsin Chen, Jyi-Tsong Lin, Yi-Chuen Eng, Hsien-Nan Chiu, Tzu-Feng Chang, Yi-Hsuan Fan, Yu-Che Chang, Kuan-Yu Lu and Chih-Hsuan Tai |
| Jun-10 | 研討會論文 | Design theory and fabrication process of 90nm Unipolar-CMOS | Jyi-Tsong Lin, Hsuan-Hsu Chen, Kuan-Yu Lu, Chih-Hung Sun, Yi-Chuen Eng, Chih-Hao Kuo, Po-Hsieh Lin, Tung-Yen Lai, Fu-Liang Yang |
| Jun-10 | 研討會論文 | Pragmatic Study of Nanowire FETs with Nonideal Gate Structure | Jyi-Tsong Lin, Chun-Yu Chen and Meng-Hsuch Chiang |
| May-10 | 研討會論文 | A 3-D Simulation Study of A Novel Source-Tied Vertical MOSFET | Chih-Hsuan Tai, Jyi-Tsong Lin, Yi-Chuen Eng, Kuan-Yu Lu, Cheng-Hsin Chen, Yu-Che Chang, and Yi-Hsuan Fan |
| May-10 | 研討會論文 | A Highly Scalable Π-Shaped Source/Drain Quasi-SOI MOS Transistor | Yi-Chuen Eng, Jyi-Tsong Lin, Yi-Hsuan Fan, Yu-Che Chang, Kuan-Yu Lu, Cheng-Hsien Chen, and Chih-Hsuan Tai |
| May-10 | 研討會論文 | A Non-Classical Body-Tied Vertical Metal-Oxide-Semiconductor Field-Effect Transistor | Kuan-Yu Lu, Jyi-Tsong Lin, Yi-Chuen Eng, Chih-Hsuan Tai, Cheng-Hsin Chen, Yu-Che Chang, and Yi-Hsuan Fan |
| May-10 | 研討會論文 | A Non-Classical Body-Tied Vertical Metal-Oxide-Semiconductor Field-Effect Transistor | Kuan-Yu Lu, Jyi-Tsong Lin, Yi-Chuen Eng, Chih-Hsuan Tai, Cheng-Hsin Chen, Yu-Che Chang, and Yi-Hsuan Fan |
| May-10 | 研討會論文 | A Non-Classical Vertical Metal-Oxide-Semiconductor Field-Effect Transistor with Body-Tied Structure | Kuan-Yu Lu, Jyi-Tsong Lin, Yi-Chuen Eng, Yu-Che Chang, Cheng-Hsin Chen, Chih-Hsuan Tai, and Yi-Hsuan Fan |
| May-10 | 研討會論文 | A Novel Source-Tied Vertical MOSFET：3-D Simulation Study | Chih-Hsuan Tai, Jyi-Tsong Lin, Yi-Chuen Eng, Kuan-Yu Lu, Cheng-Hsin Chen, Yu-Che Chang, and Yi-Hsuan Fan |
| May-10 | 研討會論文 | A Partially Air-Insulated TFT for 1T-DRAM Application | Jyi-Tsong Lin, Tzu-Feng Chang, Yi-Chuen Eng, Chih-Hung Sun, Hsien-Nan Chiu, Hsuan-Hsu Chen, Chih-Hao Kuo, and Po-Hsieh Lin |
| May-10 | 研討會論文 | A Simulation Study of a Novel Dual-Channel Body-Tied MOSFET | Yi-Hsuan Fan, Jyi-Tsong Lin, Yi Chuen Eng, Yu-Che Chang, Cheng-Hsin Chen, Kuan-Yu Lu and Chih-Hsuan Tai |
| May-10 | 研討會論文 | A Simulation Study of the Thermal Effects in an SBT Thin-Film TransistorApplications | Yi-Hsuan Fan, Jyi-Tsong Lin, Yu-Che Chang, Cheng-Hsin Chen, Kuan-Yu Lu, Chih-Hsuan Tai, and Yi-Chuen Eng |
| May-10 | 研討會論文 | A Study of bMOS Transistor with Block Oxide Length (Lbo) Effects | Yu-Che Chang, Jyi-Tsong Lin, Yi-Chuen Eng, Cheng-Hsin Chen, Kuan-Yu Lu, Chih-Hsuan Tai, and Yi-Hsuan Fan |
| May-10 | 研討會論文 | An Effect of Block Oxide Length (Lbo) in a bMOS | Yu-Che Chang, Jyi-Tsong Lin, Yi-Chuen Eng, Cheng-Hsin Chen, Kuan-Yu Lu, Chih-Hsuan Tai, and Yi-Hsuan Fan |
| May-10 | 研討會論文 | An Improved Double-Gate MOSFET Device with Self-Align Fabrication Process steps and Source-Drain Tie | Po-Hsieh Lin, Jyi-Tsong Lin,Yi-Chuen Eng |
| May-10 | 研討會論文 | An Ultimate Planar MOS Transistor for High-Performance Applications Based on Classical and Modern Techniques | Jyi-Tsong Lin, Yi-Chuen Eng, Chih-Hao Kuo, and Po-Hsieh Lin |
| May-10 | 研討會論文 | Characterization of a Body-Tied Vertical MOSFET | Kuan-Yu Lu, Jyi-Tsong Lin, Yi-Chuen Eng, Chih-Hsuan Tai, Cheng-Hsin Chen, Yu-Che Chang, and Yi-Hsuan Fan |
| May-10 | 研討會論文 | Investigation of Thermal Characteristics for an Advanced bMPI-FET 1T-DRAM Cell | Cheng-Hsin Chen, Jyi-Tsong Lin, Yi-Chuen Eng, Hsien-Nan Chiu, Tzu-Feng Chang, Chih-Hsuan Tai, Yi-Hsuan Fan, Yu-Che Chang and Kuan-Yu Lu |
| May-10 | 研討會論文 | Self-Aligned Block-Oxide Quasi-SOI MOSFETs with S/D-Tie | Chih-Hung Sun, Jyi-Tsong Lin, Yi-Chuen Eng, Tzu-Feng Chang, Po-Hiesh Lin, Hsuan-Hsu Chen, Chih-Hao Kuo, Hsien-Nan Chiu |
| May-10 | 研討會論文 | Thermal Characteristics of an Advanced bMPI-based Capacitorless DRAM Cell | Cheng-Hsin Chen, Jyi-Tsong Lin, Yi Chuen Eng, Chiu-Hsien Nan, Tzu-Feng Chang, Chih-Hsuan Tai, Yi-Hsuan Fan, Yu-Che Chang and Kuan-Yu Lu |
| Mar-10 | 研討會論文 | An Improved Self-Aligned Double-Gate MOSFET Device with Source/Drain Tie | Po-Hsieh Lin, Jyi-Tsong Lin, and Yi-Chuen Eng |
| Mar-10 | 研討會論文 | Block Oxide Length (Lbo) Effects in a bMOS Transistor | Yu-Che Chang, Jyi-Tsong Lin, Yi-Chuen Eng, Cheng-Hsin Chen, Kuan-Yu Lu |
| Jul-09 | 研討會論文 | A Novel Self-Align Double Gate MOSFET with Source/Drain Tie | Po-Hsieh Lin, Jyi-Tsong Lin, and Yi-Chuen Eng |
| Jul-09 | 研討會論文 | A simulation study of source/drain-tie effects on characteristics of self-aligned π-shaped source/drain ultrathin SOI FETs | Yi-Chuen Eng, Jyi-Tsong Lin, Tzu-Feng Chang |
| Jul-09 | 研討會論文 | Advanced Block Oxide MOSFETs for 25 nm Technology Node | Chih-Hung Sun, Jyi-Tsong Lin, Yi-Chuen Eng, Tzu-Feng Chang, Po-Hiesh Lin, Hsuan-Hsu Chen, Chih-Hao Kuo , Hsien-Nan Chiu |
| Jul-09 | 研討會論文 | Improving Reliability and Diminishing Parasitic Capacitance Effects in a Vertical Transistor with Embedded Gate | Jyi-Tsong Lin, Chih-Hao Kuo*, Tai-Yi Lee, Yi-Chuen Eng, Tzu-Feng Chang, Po-Hsieh Lin, Hsuan-Hsu Chen |
| Jul-09 | 研討會論文 | Self-Aligned SOI MOSFETs with Ω-Shaped Conductive Layer and Source/Drain-Tie | Jyi-Tsong Lin, Tzu-Feng Chang*, Yi-Chuen Eng, Hsuan-Hsu Chen, Chih-Hao Kuo, Chih-Hung Sun, Po-Hiesh Lin, Hsien-Nan Chiu |
| Jun-09 | 研討會論文 | The impact of Junction Depth on Vertical Sidewall MOSFETs with Embedded Gate | Chih-Hao Kuo, Jyi-Tsong Lin, Tai-Yi Lee, Yi-Chuen Eng, Tzu-Feng Chang, Po-Hsieh Lin, Hsuan-Hsu Chen, Chih-Hung Sun, and Hsien-Nan Chiu |
| May-09 | 研討會論文 | A Novel Double Gate MOSFET with Self-Align Process and Source/Drain Tie | Jyi-Tsong Lin, Po-Hsieh Lin, Yi-Chuen Eng |
| May-09 | 研討會論文 | A Novel Poly-Si Thin-Film Transistor with Multi-Trenched Body by Using Isotropic-etching for Suppressing Off-State Leakage | Hsien-Nan Chiu, Jyi-Tsong Lin, Yi-Chuen Eng, Po-Hiesh Lin, Tzu-Feng Chang, Chih-Hung Sun, Chih-Hao Kuo, Hsuan-Hsu Chen |
| May-09 | 研討會論文 | A Novel Poly-silicon Thin-Film Transistor with Multi-Trenched Body Formed by Using Isotropic-etching for Suppressing Off-State Leakage | Hsien-Nan Chiu, Jyi-Tsong Lin, Yi-Chuen Eng, Po-Hiesh Lin, Tzu-Feng Chang, Chih-Hung Sun, Chih-Hao Kuo, Hsuan-Hsu Chen |
| May-09 | 研討會論文 | An Improved Vertical Embedded Sidewall-Gate MOSFET for Reducing Parasitic Capacitance and Suppressing Kink Effects | Chih-Hao Kuo, Jyi-Tsong Lin, Tai-Yi Lee, Yi-Chuen Eng, Tzu-Feng Chang |
| May-09 | 研討會論文 | Future of Planar Self-Aligned Block Oxide Based MOSFET Technology | Jyi-Tsong Lin, Yi-Chuen Eng, Chih-Hao Kuo, Tzu-Feng Chang, Chih-Hung Sun, Po-Hsieh Lin, Hsien-Nan Chiu, and Hsuan-Hsu Chen |
| May-09 | 研討會論文 | Self-Aligned Silicon-On-Insulator MOSFETs with Ω-Shaped Conductive Layer | Tzu-Feng Chang, Jyi-Tsong Lin, Yi-Chuen Eng, Chih-Hung Sun, Po-Hiesh Lin, Hsien-Nan Chiu, Hsuan-Hsu Chen, Chih-Hao Kuo |
| May-09 | 研討會論文 | Simulation Study of Novel FinFET Devices with connected body | Jyi-Tsong Lin, Po-Hsieh Lin*, Yi-Chuen Eng |
| Apr-09 | 研討會論文 | A New Novel FinFET Device | Po-Hsieh Lin, Jyi-Tsong Lin, and Yi-Chuen Eng |
| Apr-09 | 研討會論文 | A Novel Double Gate MOSFET with Self-align Process and Source/Drain Tie | Po-Hsieh Lin, Jyi-Tsong Lin, and Yi-Chuen Eng |
| Apr-09 | 研討會論文 | A Novel Polysilicon Thin-Film Transistor with Multi-Trenched Body by Using Isotropic-etching for Suppressing Off-State Leakage | Hsien-Nan Chiu, Jyi-Tsong Lin, Yi-Chuen Eng, Po-Hiesh Lin, Tzu-Feng Chang |
| Apr-09 | 研討會論文 | A Simulation Study of Source/Drain-Tie Effects on the Short-Channel Characteristics of SA-ΠFETs | Jyi-Tsong Lin, and Yi-Chuen Eng |
| Apr-09 | 研討會論文 | A Vertical Transistor with Embedded Gate for Reducing Parasitic Overlap Capacitance | Chih-Hao Kuo, Jyi-Tsong Lin, Tai-Yi Lee, Yi-Chuen Eng, Tzu-Feng Chang |
| Apr-09 | 研討會論文 | Self-Aligned Silicon-On-Insulator Transistors with Ω-Shaped Conductive Layer and Source/Drain-Tie: A Simulation Study | Tzu-Feng Chang*, Jyi-Tsong Lin, Yi-Chuen Eng, Chih-Hao Kuo, Chih-Hung Sun, Po-Hiesh Lin, Hsien-Nan Chiu, Hsuan-Hsu Chen |
| Apr-09 | 研討會論文 | Study of bMOS and bMPI for 25 nm technology node | Chih-Hung Sun, Jyi-Tsong Lin, Yi-Chuen Eng, Tzu-Feng Chang, Po-Hiesh Lin, Hsuan-Hsu Chen, Chih-Hao Kuo , Hsien-Nan Chiu |
| Mar-09 | 研討會論文 | Study of New Novel FinFET Device with Its Bodies been Connected | Jyi-Tsong Lin, Po-Hsieh Lin, and Yi-Chuen Eng |
| Nov-08 | 研討會論文 | A New Double-Gate Vertical MOSFET with Native tie for 1-T DRAM | Ying-Chieh Tsai, Jyi-Tsong Lin, Yi-Chuen Eng, Shiang-Shi Kang, Yi-Ming Tseng and Hung-Jen Tseng |
| Nov-08 | 研討會論文 | HBO Effects in Self-Aligned Multi-Substrate Contact Field-Effect Transistors | Yi-Chuen Eng, Jyi-Tsong Lin*, Yi-Ming Tseng, Hung-Jen Tseng, Ying-Chieh Tsai, Po-Hiesh Lin, Shiang-Shi Kang, and Ting-Jyun Guan |
| Oct-08 | 研討會論文 | A New Process for Self-aligned Silicon-On-Insulator with Block Oxide and Its Memory Application for 1T-DRAM | Yi-Ming Tseng, Jyi-Tsong Lin, Yi-Chuen Eng, Shiang-Shi Kang, Hung-Jen Tseng, Ying-Chieh Tsai |
| Oct-08 | 研討會論文 | The Influence of the Source/Drain-tie Length in a Novel Self-Aligned S/D tie SOI for Improving Self-heating | Jyi-Tsong Lin, Shiang-Shi Kang, Yi-Chuen Eng, Yi-Ming Tseng, Ying-Chieh Tasi, Hung-Jen Tseng |
| Aug-08 | 研討會論文 | A Novel Pseudo Tri-Gate Vertical MOSFET with Source/Drain tie | Jyi-Tsong Lin, Ying-Chieh Tsai, Yi-Chuen Eng, Yi-Ming Tseng, Shiang-Shi Kang |
| Aug-08 | 研討會論文 | Simulation of the Multi-Source/Drain SOI MOSFET | Jyi-Tsong Lin, Po-Hsieh Lin, Yi-Chuen Eng, and Shiang-Shi Kang |
| Jun-08 | 研討會論文 | A Study of LBO Effects in a 40 nm SA-MSCFET | Jyi-Tsong Lin, Yi-Chuen Eng, and Shiang-Shi Kang |
| Jun-08 | 研討會論文 | An Advanced Non-classical Self-aligned Quasi-SOI MOSFET with π-shaped Semiconductor Conductive Layer to Ease Ultra-shallow Junction Requirement | Jyi-Tsong Lin, Yi-Chuen Eng, Ying-Chieh Tsai, Hung-Jen Tseng, Yi-Ming Tseng, Po-Hsieh Lin |
| Jun-08 | 研討會論文 | An SOI-based Self-aligned Quasi-SOI MOSFET with π-shaped Semiconductor Conductive Layer | Yi-Chuen Eng, Jyi-Tsong Lin, and Shiang-Shi Kang |
| May-08 | 研討會論文 | A Compensation Threshold Voltage Shift Pixel Circuit For Active Matrix Organic Light Emitting Diode | Cheng-Neng Wen, Jyi-Tsong Lin |
| May-08 | 研討會論文 | A Novel Multi-Source/Drain SOI MOSFET | Jyi-Tsong Lin, Po-Hsieh Lin, Yi-Chuen Eng, Ying-Chieh Tasi, Hung-Jen Tseng,Yi-Ming Tseng |
| May-08 | 研討會論文 | A Novel Pseudo Tri-Gate VMOS for Enhancing Thermal Stability | Jyi-Tsong Lin, Ying-Chieh Tsai, and Yi-Chuen Eng |
| May-08 | 研討會論文 | A Novel Pseudo Tri-Gate Vertical MOSFET with Source/Drain tie | Jyi-Tsong Lin, Ying-Chieh Tsai, and Yi-Chuen Eng |
| May-08 | 研討會論文 | A Novel SOI MOSFET with Multi-Source/Drain | Jyi-Tsong Lin, Po-Hsieh Lin, and Yi-Chuen Eng |
| May-08 | 研討會論文 | A Novel Structural Polysilicon Thin-Film Transistor with Trenched Body Technology | Jyi-Tsong Lin, Kuo-Dong Huang and Bao-Tang Jheng |
| May-08 | 研討會論文 | A Novel Vertical Sidewall MOSFET Using Smart Source/Body Contact without Floating-Body Effect | Tai-Yi Lee, Jyi-Tsong Lin, Yi-Chuen Eng , Kao-Cheng Lin |
| May-08 | 研討會論文 | A Novel Vertical Sidewall MOSFETs Using Smart Source/Body Contact without Floating-Body Effect | Tai-Yi Lee, Jyi-Tsong Lin, Po-Hsieh Lin, Yi-Chuen Eng |
| May-08 | 研討會論文 | Misalignment of the gate to the body in a bSPIFET | Jyi-Tsong Lin, Hung-Jen Tseng, Yi-Chuen Eng, Yi-Ming Tseng, Shiang-Shi Kang, Ying-Chieh Tasi |
| May-08 | 研討會論文 | Partially Depleted Silicon-On-Insulator with Block Oxide (bPDSOI) for 1T-DRAM | Jyi-Tsong Lin, Yi-Ming Tseng, Yi-Chuen Eng, Shiang-Shi Kang, Hung-Jen Tseng, Ying-Chieh Tsai, and Po-Hsieh Lin |
| May-08 | 研討會論文 | Self-aligned π-shaped Source/Drain Ultra-thin SOI MOSFETs | Yi-Chuen Eng, Jyi-Tsong Lin, Hau-Yuan Huang, Shiang-Shi Kang, Po-Hsieh Lin, Kung-Kai Kao |
| May-08 | 研討會論文 | Source/Drain-tied Bottom Gate MOSFET for Device Reliability Improvement | Jeng-Da Lin, Jyi-Tsong Lin, Kung-Kai Kao, Shiang-Shi Kang, Yi-Chuen Eng, Po-Hsieh Lin |
| May-08 | 研討會論文 | The Effect of Block Oxide Height on a Self-aligned Source/Drain-tied nBOFET | Jyi-Tsong Lin, Yi-Chuen Eng, Shiang-Shi Kang, Po-Hsieh Lin, Yi-Ming Tzeng, Jeng-Da Lin |
| May-08 | 研討會論文 | The Influence of the Source/drain-tie Length on the SOI Based Transistors | Jyi-Tsong Lin, Shiang-Shi Kang, Yi-Chuen Eng, Yi-Ming Tseng, Ying-Chieh Tsai, Hung-Jen Tseng |
| May-08 | 研討會論文 | The Novel Embedded Vertical Sidewall MOSFETs | Jyi-Tsong Lin, Tai-Yi Lee, and Kao-Cheng Lin |
| May-08 | 研討會論文 | The Study of Influence of the Source/drain-tie Length in a S/D tie SOI for Improving Self-Heatin | Jyi-Tsong Lin, Shiang-Shi Kang, and Yi-Chuen Eng |
| May-08 | 研討會論文 | The misalignment between the Body and Gate in a bSPIFET | Jyi-Tsong Lin, Hung-Jen Tseng, Yi-Chuen Eng, Yi-Ming Tseng, Shiang-Shi Kang, Ying-Chieh Tsai, Bao-Tang Jheng, and Po-Hsieh Lin |
| Apr-08 | 研討會論文 | Self-aligned Partially Depleted Silicon-On-Insulator with Block Oxide (bPDSOI) for 1T-DRAM | Jyi-Tsong Lin, Yi-Ming Tseng, Yi-Chuen Eng, Shiang-Shi Kang, Hung-Jen Tseng, and Ying-Chieh Tsai |
| Dec-07 | 研討會論文 | A Novel Polysilicon Thin-Film Transistor with Multi-Trenched Body for Suppressing Off-State Leakage | Jyi-Tsong Lin, Kuo-Dong Huang |
| Dec-07 | 研討會論文 | Impact of Source/Drain Tie on 30 nm Bottom Gate MOSFETs | Jyi-Tsong Lin, Jeng-Da Lin, Shiang-Shi Kang, Hau-Yuan Huang, Kung-Kai Kao |
| Nov-07 | 研討會論文 | A Non-Classical Polysilicon Thin-Film Transistor with Symmetric Trenched Body | Jyi-Tsong Lin, Kuo-Dong Huang |
| Nov-07 | 研討會論文 | A Novel Middle-Gate-Double-Channel FET for high Reliability Use | Hau-Yuan Huang, Jyi-Tsong Lin, Yi-Chuen Eng, Jeng-Da Lin, and Kung-Kai Kao |
| Nov-07 | 研討會論文 | Characteristics Study of Pillar Field-Effect Transistor for Future High Reliability application | Jyi-Tsong Lin, Kung-Kai Kao, Jeng-Da Lin, Yi-Chuen Eng, Shiang-Shi Kang, and Hau-Yuan Huang |
| Sep-07 | 研討會論文 | Improvement of Self-heating Effects in Nanoscale Multi-substrate Contact Field-effect Transistors | Yi-Chuen Eng and Jyi-Tsong Lin |
| Sep-07 | 研討會論文 | Self-aligned Block Oxide Process for bSPIFETs | Jyi-Tsong Lin and Yi-Chuen Eng |
| Aug-07 | 研討會論文 | Novel Devices Merging RITD and CMOS for Future VLSI Use | Jyi-Tsong Lin, Wei-Chin Lin, and Chao-Yu Hou |
| Aug-07 | 研討會論文 | Self–Aligned Double Bits SONOS Cell and Its Memory Circuit Design | Jyi-Tsong Lin, Wei-Ching Lin, and Ho-Lin Lee |
| Jul-07 | 研討會論文 | Advanced π-FET Technology for 45 nm Technology Node | Yi-Chuen Eng and Jyi-Tsong Lin |
| Jul-07 | 研討會論文 | Misalignment of the Block Oxide Height in Self-aligned Source/Drain-tied bFDSOI-FET | Jyi-Tsong Lin, Yi-Chuen Eng, Kung-Kai Kao, Hau-Yuan Huang, Jeng-Da Lin, Shiang-Shi Kang |
| Jun-07 | 研討會論文 | Oxide Islands Design for Elimination of Ultra-shallow Junction Formation | Jyi-Tsong Lin and Yi-Chuen Eng |
| May-07 | 研討會論文 | A High Performance Thin-Film Transistor Built on Block-Oxide N-Channel Polycrystalline Silicon | Jyi-Tsong Lin, Kuo-Dong Huang, and Yu-Chi Kang |
| May-07 | 研討會論文 | A New GAA Manufacture Process and Performance Evaluation | Jyi-Tsong Lin, Ho-Ting Chen, and Wei-Chin Lin |
| May-07 | 研討會論文 | A New Self-Aligned Double-Gate Thin-Film Transistor With π-Shaped Source/Drain Regions | Jyi-Tsong Lin, John Chen, Yi-Chuen Eng, and Wei-Jhe Yang |
| May-07 | 研討會論文 | A Potential U Cave Integrated MOS Devices and Discussion | Jyi-Tsong Lin, Cheng-heng Liu, and Wei-Chin Lin |
| May-07 | 研討會論文 | An Assessment of New SRAM Cell Fabrication and Working Theory | Jyi-Tsong Lin, Jian-Hong Song, and Wei-Ching Lin |
| May-07 | 研討會論文 | Investigation Of The Novel Device Which Sets MOSFET With Resonance Intra-Band Tunneling Diode | Jyi-Tsong Lin, Chao-Yu Hou, and Wei-Chin Lin |
| May-07 | 研討會論文 | Investigation of the Novel attribution in A new Vertical MOSFET with Upper and Internal L-shape Buried Oxide | Jyi-Tsong Lin, Tai-Yi Lee, Kao-Cheng Lin, and Yu-Sheng Chen |
| May-07 | 研討會論文 | Misalignment of the Block Oxide Height in Self-Aligned bSPIFET | Jyi-Tsong Lin and Yi-Chuen Eng |
| May-07 | 研討會論文 | Self-aligned Block Oxide Enclosed Body Process for FDSOI Devices | Yi-Chuen Eng, and Jyi-Tsong Lin |
| May-07 | 研討會論文 | Self-aligned Block Oxide Process for bFDSOI Devices | Yi-Chuen Eng and Jyi-Tsong Lin |
| May-07 | 研討會論文 | The Impact of Block Oxide Height in Self-Aligned bSPIFET | Jyi-Tsong Lin, and Yi-Chuen Eng |
| Jan-07 | 研討會論文 | Analysis of Si-body Thickness Variation for a new 40 nm Gate Length bFDSOI | Jyi-Tsong Lin, Yi-Chuen Eng, Tai-Yi Lee, and Kao-Cheng Lin |
| Dec-06 | 研討會論文 | Analysis of the Block Oxide Width Variations in a Body-tied Nanodevice | Jyi-Tsong Lin, and Yi-Chuen Eng |
| Dec-06 | 研討會論文 | Fabrication of Polysilicon Thin-Film Transistor Built on Poly Buffer LOCOS | Jyi-Tsong Lin, Kuo-Dong Huang, Shih-Tsong Lin, Chu-Lun Wu, Chin-Lung Sung, Ya-Chang Chuo |
| Dec-06 | 研討會論文 | Fabrication of the Bottom Gate Thin Film Transistor with Smart Body Tie | Jyi-Tsong Lin, Kuo-Dong Huang, Shih-Tsong Lin, Shu-Fen Hu |
| Nov-06 | 研討會論文 | An Investigation Of The Self-Aligned And Smart-Body-Tied Bottom-Gate Thin Film Transistor | Jyi-Tsong Lin, Wei-Jhe Yang, Jhen-Chen, and Yi-Chuen Eng |
| Nov-06 | 研討會論文 | Investigation Of The Novel Attribution In A New Vertical MOSFET With Upper And Internal L-Shape Buried Oxide | Jyi-Tsong Lin, Yu-Sheng Chen, Tai-Yi Lee, and Kao-Cheng Lin |
| Nov-06 | 研討會論文 | The Fabrication of Block-Oxide Thin-Film Transistor with Superior Subthreshold Characteristics | Jyi-Tsong Lin, and Kuo-Dong Huang |
| Oct-06 | 研討會論文 | A Nanoscale bSPIFET to Overcome CMOS Scaling | Jyi-Tsong Lin, Yi-Chuen Eng, Tai-Yi Lee, and Kao-Cheng Lin |
| Oct-06 | 研討會論文 | An Investigation of the effects of Si thickness-induced variation of the electrical characteristics in FDSOI with block oxide | Yi-Chuen Eng, Jyi-Tsong Lin, Kuo-Dong Huang, Tai-Yi Lee, and Kao-Cheng Lin |
| Oct-06 | 研討會論文 | Characterization of the Self-aligned Pseudo-SOI Device Structures | Jyi-Tsong Lin and Yi-Chuen Eng |
| Aug-06 | 研討會論文 | A New 1T DRAM Cell With Enhanced Floating Body Effect | yi-Tsong Lin, and Mike Chang, |
| Jul-06 | 研討會論文 | HIGH PERFORMANCE THIN-FILM TRANSISTOR WITH L-SHAPED BLOCK OXIDE | Jyi-Tsong Lin, Yi-Chuen Eng, Tai-Yi Lee, Kao-Cheng Lin, and Kuo-Dong Huang |
| Jul-06 | 研討會論文 | Ultra-Short-Channel Characteristics of Planar MOSFETs with Block Oxide | Jyi-Tsong Lin, Yi-Chuen Eng, Kuo-Dong Huang, Tai-Yi Lee, and Kao-Cheng Lin |
| May-06 | 研討會論文 | A Kink-Free Bottom Gate Poly-Si Thin-Film Transistor with Smart Body Tie | Jyi-Tsong Lin, Kuo-Dong Huang and Shih-Tsong Lin |
| May-06 | 研討會論文 | A Kink-Free Polysilicon Thin-Film Transistor Built on Local Oxidation of Silicon (LOCOS) | Jyi-Tsong Lin, Kuo-Dong Huang, and Chu-Lun Wu |
| May-06 | 研討會論文 | A Nano Quasi-SOI MOSFET with π-shaped Semiconductor Layer | Yi-Chuen Eng, Jyi-Tsong Lin, Tai-Yi Lee, and Kao-Cheng Lin |
| May-06 | 研討會論文 | A Novel Bottom Gate Polysilicon Thin-Film Transistor with Smart Body Tie | Jyi-Tsong Lin1, Kuo-Dong Huang2, Shih-Tsong Lin |
| May-06 | 研討會論文 | A Novel Device Architecture: Silicon on Partial Insulator with Block Oxide | Jyi-Tsong Lin, Yi-Chuen Eng, Tai-Yi Lee, and Kao-Cheng Lin |
| May-06 | 研討會論文 | A Novel FDSOI MOSFET with Block Oxide Enclosed Body, | Jyi-Tsong Lin, Yi-Chuen Eng, Kuo-Dong Huang, Tai-Yi Lee, and Kao-Cheng Lin, |
| May-06 | 研討會論文 | A Novel Vertical MOSFET with Smart Source/ Body Contact | Tai-Yi Lee, Jyi-Tsong Lin, Yi-Chuen Eng, and Kao-Cheng Lin |
| May-06 | 研討會論文 | An Impact of Block Oxide on 50 nm Gate Length Planar MOSFETs | Jyi-Tsong Lin, Yi-Chuen Eng, Tai-Yi Lee, Kao-Cheng Lin, and Kuo-Dong Huang |
| May-06 | 研討會論文 | Elimination of Floating body Effect and Thermal Instability in a Nano Quasi-SOI MOSFET with π-shaped Semiconductor Layer | Jyi-Tsong Lin, Yi-Chuen Eng, Tai-Yi Lee, and Kao-Cheng Lin |
| May-06 | 研討會論文 | Investigation of a Pseudo Vertical SOI MOSFET With L-Shaped Block Layer | Jyi-Tsong Lin, Kao-Cheng Lin, Tai-Yi Lee, and Yi-Chuen Eng |
| May-06 | 研討會論文 | Investigation of the Novel Attributes of a Vertical MOSFET Device with Internal Block Layer: a 2D Simulation Study | Jyi-Tsong Lin, Kao-Cheng Lin, Tai-Yi Lee, Yi-Chuen Eng |
| May-06 | 研討會論文 | The Fabrication of Single Electron Transistor by Polysilicon Thin Film and Point-Contact | Kuo-Dong Huang1, Jyi-Tsong Lin |
| Dec-05 | 研討會論文 | A Recessed Multi-Gate PD SOI MOSFET and Its Threshold Voltage | Jyi-Tsong Lin and Kuo-ying Huang |
| Aug-05 | 研討會論文 | A 1.1V 25μW Sigma-Delta modulator | Shu-Ting Yang, and Jyi-Tsong Lin |
| Aug-05 | 研討會論文 | A 6-bit SAR pipelined ADC using improved TIQ technology | Yan-Huei Lee, and Jyi-Tsong Lin |
| Aug-05 | 研討會論文 | A LOW-POWER LOW-COST 6-BIT 256MHZS/S ANALOG TO DIGITAL CONVERTER USING SELECTIVE REFERENCE VOLTAGE | Chung-Hsiao Hsieh, and Jyi-Tsong Lin |
| May-05 | 研討會論文 | A New MOSFET with Block Spacer Enclosed Body | Jyi-Tsong Lin, and Eng Yi Chuen |
| May-05 | 研討會論文 | A new 1T DRAM Cell With Enhanced Floating Body Effect | Jyi-Tsong Lin, and Mike Chang |
| May-05 | 研討會論文 | Bottom Gate SOI MOSFET with Smart Body Tie | Jyi-Tsong Lin, and Shih-Tsong Lin |
| May-05 | 研討會論文 | New Fabrication Method of Silicon-On-Insulator (SOI) MOSFET | Jyi-Tsong Lin, and Chu-Lun Wu |
| May-05 | 研討會論文 | New Fabrication Method of Silicon-On-Insulator (SOI) MOSFET | Jyi-Tsong Lin, and Chu-Lun Wu |
| May-05 | 研討會論文 | Single Electron Device Operated in Room Temperature | Jyi Tsong Lin, and Kuo-Dong Huang |
| May-05 | 研討會論文 | Using double-spacer technique to Fabricate Silicon on Partial Insulator with block oxide | Jyi Tsong Lin, Yi-Chuen Eng, and Chun-Ming Pan |
| Dec-04 | 研討會論文 | A Recessed Multi-Gate PD SOI MOSFET and Its Threshold Voltage | Jyi-Tsong Lin and Kuo-ying Huang, |
| Dec-04 | 研討會論文 | Multiple Dots Effect Fabricated on Point-Contact Single Electron Transistor, | Kuo-Dong Huang, Jyi-Tsong Lin, Yue-Min Wan, S. F. Hu and C. L. Sung, |
| Oct-04 | 研討會論文 | Multi-Gate SOI MOSFET for 3D IC fabrication | Jyi-Tsong Lin and Jian-Han Huang, |
| Aug-04 | 研討會論文 | A 2.5V 8-bit 100MHzS/s 15.3mW Cur rent Mode Folding and Interpolation Analog to Digital Conver ter Using Back-end Amplifier | Shi-Xuan, and Jyi Tsong Lin |
| Aug-04 | 研討會論文 | A 3.3V 10-bit 50-MS/s Pipelined Analog-to-Digital Converter with Low-Deviation MDAC | Chun-Ta Wang, and Jyi Tsong Lin |
| May-04 | 研討會論文 | A 71nm Cross-Gate SOI MOSFET for 3D IC fabricated on a bulk wafer | Jyi Tsong Lin, and Jian-Han Huang |
| Mar-03 | 研討會論文 | High quality SGOI (SiGe-On-Insulator) wafer fabrication by Ge-Condensation | Pai-Chin Chen, Jyi Tsong Lin, Yuan-Liang Liu, and Zhao-Xin Jian |
| Aug-02 | 研討會論文 | High Speed Circuit Schemes for a Low Supply Voltage DRAM | Jyi-Tsong Lin, and Shih-Zung Wei |
| May-02 | 研討會論文 | An SOI MOSFET with Triple Recessed Body and Multi-Gate | Jyi-Tsong Lin, Ping-Shin Jue, Yan-Youg Xu, Shih-chang Chang, and Kuo-ying Huang |
| Dec-01 | 研討會論文 | Self-Heating And Bipolor Snap-Breakdown of A Triple Recessed Multi-Gate SOI MOSFE | Jyi-Tsong Lin, Ping-Shin Jue, Shih-chang Chang, Kuo-ying Huang, |
| Oct-01 | 研討會論文 | Recessed Multi-Gate SOI MOSFET’s in Deep Decanonometer regime | Jyi-Tsong Lin, Shih-Chang Chang, Kuo-Ying Huang, Yan-Youg Xu, Ping-Shin Jue, |
| Mar-00 | 研討會論文 | A NEW GCP CELL TECHNOLOGY FOR DRAM DESIGN | Harn-Bor Yang and Jyi-Tsong Lin |
| Mar-00 | 研討會論文 | AN INITIAL OVERDRIVEN SENSE AMPLIFIER FOR LOW VOLTAGE DRAMs | Jyi-Tsong Lin and Cheng-Chih Hsu |
| Aug-99 | 研討會論文 | The I/O Line Boosted Sensing Scheme for High Performance DRAMs | Jyi-Tsong Lin, and Cheng-Chih Hsu |
| Aug-98 | 研討會論文 | A New Word Line Driver for Low Power DRAM's | Jyi-Tsong Lin, and Lucas Tsai |
| Sep-95 | 研討會論文 | A Simple General SOI Model for Efficient Circuit Simulation | Jyi-Tsong Lin |
| Oct-94 | 研討會論文 | Parameter Characterization of Double Gate Ultra-Thin SOI MOSFET | Jyi-Tsong Lin |
| Aug-94 | 研討會論文 | A New DC Current Characteristic Model of SOI MOSFETS for Circuit Simulation | Jyi-Tsong Lin, and Chung-Ming Lee |
| Aug-94 | 研討會論文 | An Efficient SOI MOSFET's Model for SPICE-DC Analysis | Jyi-Tsong Lin, and King-Yu Lu |
| Oct-93 | 研討會論文 | New Concepts of SOI Modelling for Use in Circuit Simulator | Jyi-Tsong Lin and Ken G. Nichols |
| Jun-93 | 研討會論文 | Reliability of Circuit-level Simulation | Ken G. Nicholas, Jyi-Tsong Lin, Andrew D. Brown, Tom Kazmierski and Mark Zwolinski, |
| May-85 | 研討會論文 | A Logic/Timing Simulator for Digital MOSIC | Jyi-Tsong Lin, Chein-Wei Jen, Wen-Zen Shen and Chung-Len Lee, |
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